diff options
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 82ec2da453..fdc5fcc419 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -536,7 +536,18 @@ static void glk_fsp_silicon_init_params_cb( #if CONFIG(SOC_INTEL_GEMINILAKE) uint8_t port; + /* + * UsbPerPortCtl was retired in Fsp 2.0.0+, so PDO programming must be + * enabled to configure individual ports in what Fsp thinks is PEI. + */ + silconfig->UsbPdoProgramming = cfg->usb_config_override; + for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { + if (cfg->usb_config_override) { + silconfig->PortUsb20Enable[port] = cfg->usb2_port[port].enable; + silconfig->PortUs20bOverCurrentPin[port] = cfg->usb2_port[port].oc_pin; + } + if (!cfg->usb2eye[port].Usb20OverrideEn) continue; @@ -550,6 +561,13 @@ static void glk_fsp_silicon_init_params_cb( cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; } + if (cfg->usb_config_override) { + for (port = 0; port < APOLLOLAKE_USB3_PORT_MAX; port++) { + silconfig->PortUsb30Enable[port] = cfg->usb3_port[port].enable; + silconfig->PortUs30bOverCurrentPin[port] = cfg->usb3_port[port].oc_pin; + } + } + silconfig->Gmm = is_devfn_enabled(SA_GLK_DEVFN_GMM); /* On Geminilake, we need to override the default FSP PCIe de-emphasis |