diff options
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/bootblock.c | 13 | ||||
| -rw-r--r-- | src/superio/Kconfig | 3 | ||||
| -rw-r--r-- | src/superio/smsc/Kconfig | 1 |
3 files changed, 14 insertions, 3 deletions
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 8ed198a9e4..d21b4fdbfd 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -97,10 +97,17 @@ static void enable_clocks(void) reg8 &= ~(1 << 1); outb(reg8, 0xCD7); - // Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz) + // Program SB800 MiscClkCntrl register to configure clock output on the + // 14M_25M_48M_OSC ball usually used for the Super-I/O. + // Almost all SIOs need 48 MHz, only the SMSC SCH311x wants 14 MHz, + // which is the SB800's power up default. We could switch back to 14 + // in the mainboard's romstage.c, but then the clock frequency would + // change twice. reg32 = *acpi_mmio; - reg32 &= ~((1 << 0) | (1 << 2)); - reg32 |= 1 << 1; + reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default) +#if !CONFIG_SUPERIO_WANTS_14MHZ_CLOCK + reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz +#endif *acpi_mmio = reg32; } diff --git a/src/superio/Kconfig b/src/superio/Kconfig index 4e05a8ef35..32e60bb367 100644 --- a/src/superio/Kconfig +++ b/src/superio/Kconfig @@ -17,6 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +config SUPERIO_WANTS_14MHZ_CLOCK + bool + source src/superio/fintek/Kconfig source src/superio/intel/Kconfig source src/superio/ite/Kconfig diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index f863b3ed38..6aaa1127e9 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -44,6 +44,7 @@ config SUPERIO_SMSC_MEC1308 bool config SUPERIO_SMSC_SMSCSUPERIO bool + select SUPERIO_WANTS_14MHZ_CLOCK config SUPERIO_SMSC_SIO1036 bool config SUPERIO_SMSC_SCH4037 |