diff options
| -rw-r--r-- | src/mainboard/google/dedede/chromeos.c | 3 | ||||
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/gpio.c | 4 | ||||
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h | 2 |
3 files changed, 6 insertions, 3 deletions
diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index a9cc602e8d..3f0cad5a99 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -23,8 +23,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { - /* No write protect */ - return 0; + return gpio_get(GPIO_PCH_WP); } void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 6adb35ba9d..1b3e015c78 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -119,7 +119,7 @@ static const struct pad_config gpio_table[] = { /* C10 : GPP_C10/UART0_RTSB */ PAD_NC(GPP_C10, NONE), /* C11 : AP_WP_OD */ - PAD_NC(GPP_C11, NONE), + PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* C12 : AP_PEN_DET_ODL */ PAD_NC(GPP_C12, NONE), /* C13 : GPP_C13/UART1_TXD */ @@ -444,6 +444,8 @@ const struct pad_config *__weak variant_sleep_gpio_table(size_t *num) } static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME), }; const struct cros_gpio *__weak variant_cros_gpios(size_t *num) diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h index 98e4b277f7..fac834288d 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h @@ -14,6 +14,8 @@ /* eSPI virtual wire reporting */ #define EC_SCI_GPI GPE0_ESPI +#define GPIO_PCH_WP GPP_C11 + /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK |