diff options
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 5d717b8e54..0ab7c8a87a 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -96,6 +96,9 @@ chip soc/intel/alderlake # Disable SaGV reordering operation to start with SaGV point 4 and reduce boot time. register "disable_sagv_reorder" = "true" + # Disable hwp scalability tracking. + register "enable_hwp_scalability_tracking" = "false" + # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. |