diff options
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss_pcierp.asl | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 6b26231c1b..2d40dc31e4 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -6,19 +6,19 @@ * port of the USB4/TBT topology. */ /* Number of microseconds to wait after a conventional reset */ -#define FW_RESET_TIME 50000 +#define FW_RESET_TIME 50000 /* Number of microseconds to wait after data link layer active report */ -#define FW_DL_UP_TIME 1 +#define FW_DL_UP_TIME 1 /* Number of microseconds to wait after a function level reset */ -#define FW_FLR_RESET_TIME 1 +#define FW_FLR_RESET_TIME 1 /* Number of microseconds to wait from D3 hot to D0 transition */ -#define FW_D3HOT_TO_D0_TIME 50000 +#define FW_D3HOT_TO_D0_TIME 50000 /* Number of microseconds to wait after setting the VF enable bit */ -#define FW_VF_ENABLE_TIME 1 +#define FW_VF_ENABLE_TIME 1 OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800) Field (PXCS, AnyAcc, NoLock, Preserve) |