diff options
| -rw-r--r-- | src/arch/x86/Kconfig | 7 | ||||
| -rw-r--r-- | src/arch/x86/Makefile.inc | 6 | ||||
| -rw-r--r-- | src/arch/x86/cf9_reset.c | 65 | ||||
| -rw-r--r-- | src/arch/x86/include/cf9_reset.h | 40 |
4 files changed, 118 insertions, 0 deletions
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 46e0c2d368..ff26a15449 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -315,3 +315,10 @@ config IDT_IN_EVERY_STAGE bool default n depends on ARCH_X86 + +config HAVE_CF9_RESET + bool + +config HAVE_CF9_RESET_PREPARE + bool + depends on HAVE_CF9_RESET diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7f85b6a3e6..730bc838fb 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -43,6 +43,12 @@ cbfs-files-$(CONFIG_VGA_BIOS) += pci$(stripped_vgabios_id).rom pci$(stripped_vgabios_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_FILE)) pci$(stripped_vgabios_id).rom-type := optionrom +verstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c +bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c +romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c +ramstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c +postcar-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c + ############################################################################### # common support for early assembly includes ############################################################################### diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c new file mode 100644 index 0000000000..c28e4488a6 --- /dev/null +++ b/src/arch/x86/cf9_reset.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <arch/cache.h> +#include <cf9_reset.h> +#include <console/console.h> +#include <halt.h> +#include <reset.h> + +/* + * A system reset in terms of the CF9 register asserts the INIT# + * signal to reset the CPU along the PLTRST# signal to reset other + * board components. It is usually the hardest reset type that + * does not power cycle the board. Thus, it could be called a + * "warm reset". + */ +void do_system_reset(void) +{ + dcache_clean_all(); + outb(SYS_RST, RST_CNT); + outb(RST_CPU | SYS_RST, RST_CNT); +} + +/* + * A full reset in terms of the CF9 register triggers a power cycle + * (i.e. S0 -> S5 -> S0 transition). Thus, it could be called a + * "cold reset". + * Note: Not all x86 implementations comply with this defitinion, + * some may require additional configuration to power cycle. + */ +void do_full_reset(void) +{ + dcache_clean_all(); + outb(FULL_RST | SYS_RST, RST_CNT); + outb(FULL_RST | RST_CPU | SYS_RST, RST_CNT); +} + +void system_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + cf9_reset_prepare(); + do_system_reset(); + halt(); +} + +void full_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + cf9_reset_prepare(); + do_full_reset(); + halt(); +} diff --git a/src/arch/x86/include/cf9_reset.h b/src/arch/x86/include/cf9_reset.h new file mode 100644 index 0000000000..c0dcc92bd1 --- /dev/null +++ b/src/arch/x86/include/cf9_reset.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef X86_CF9_RESET_H +#define X86_CF9_RESET_H + +/* Reset control port */ +#define RST_CNT 0xcf9 +#define FULL_RST (1 << 3) +#define RST_CPU (1 << 2) +#define SYS_RST (1 << 1) + +/* Implement the bare reset, i.e. write to cf9. */ +void do_system_reset(void); +void do_full_reset(void); + +/* Called by functions below before reset. */ +#if IS_ENABLED(CONFIG_HAVE_CF9_RESET_PREPARE) +void cf9_reset_prepare(void); +#else +static inline void cf9_reset_prepare(void) {} +#endif + +/* Prepare for reset, run do_*_reset(), halt. */ +__noreturn void system_reset(void); +__noreturn void full_reset(void); + +#endif /* X86_CF9_RESET_H */ |