diff options
| -rw-r--r-- | src/soc/amd/mendocino/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/early_fch.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/include/soc/stb.h | 9 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/romstage.c | 4 |
4 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 9caee1eb5e..c03dbe22a3 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -84,6 +84,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_STB select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE diff --git a/src/soc/amd/mendocino/early_fch.c b/src/soc/amd/mendocino/early_fch.c index fb359b33b3..a9aec09df0 100644 --- a/src/soc/amd/mendocino/early_fch.c +++ b/src/soc/amd/mendocino/early_fch.c @@ -9,6 +9,7 @@ #include <amdblocks/lpc.h> #include <amdblocks/pmlib.h> #include <amdblocks/smbus.h> +#include <amdblocks/stb.h> #include <amdblocks/uart.h> #include <soc/i2c.h> #include <soc/southbridge.h> @@ -54,6 +55,9 @@ void fch_pre_init(void) /* After console init */ void fch_early_init(void) { + if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE)) + write_stb_to_console(); + reset_i2c_peripherals(); pm_set_power_failure_state(); fch_print_pmxc0_status(); diff --git a/src/soc/amd/mendocino/include/soc/stb.h b/src/soc/amd/mendocino/include/soc/stb.h new file mode 100644 index 0000000000..cba1d0a9e5 --- /dev/null +++ b/src/soc/amd/mendocino/include/soc/stb.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_MENDOCINO_STB_H +#define AMD_MENDOCINO_STB_H + +#define STB_CFG_SMN_ADDR 0x3E00000 +#define AMD_STB_SDRAM_FIFO_SIZE 2048 + +#endif /* AMD_MENDOCINO_STB_H */ diff --git a/src/soc/amd/mendocino/romstage.c b/src/soc/amd/mendocino/romstage.c index 9f2be8ee51..dfec897c03 100644 --- a/src/soc/amd/mendocino/romstage.c +++ b/src/soc/amd/mendocino/romstage.c @@ -6,6 +6,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/stb.h> #include <arch/cpu.h> #include <console/console.h> #include <fsp/api.h> @@ -16,6 +17,9 @@ void __noreturn romstage_main(void) { post_code(0x40); + if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE)) + write_stb_to_console(); + /* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); |