diff options
12 files changed, 8 insertions, 30 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 643bdc1bf7..aeab2d4bf2 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -130,7 +130,7 @@ chip soc/intel/tigerlake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF + device pci 04.0 off end # DPTF device pci 05.0 off end # IPU device pci 06.0 off end # PEG60 device pci 07.0 on end # TBT_PCIe0 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ca9661f09f..1958e99791 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -295,8 +295,6 @@ chip soc/intel/tigerlake .tdp_pl4 = 83, }" - register "Device4Enable" = "1" - register "tcc_offset" = "10" # TCC of 90 register "CnviBtCore" = "true" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 0e34eb2663..47c4368a52 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -119,9 +119,6 @@ chip soc/intel/tigerlake # Enable DPTF register "dptf_enable" = "1" - # Enable Processor Thermal Control - register "Device4Enable" = "1" - # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 15, diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 17af01aaeb..cd5493bc30 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -123,9 +123,6 @@ chip soc/intel/tigerlake # Enable DPTF register "dptf_enable" = "1" - # Enable Processor Thermal Control - register "Device4Enable" = "1" - # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 9, diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index 5c55dce396..a3fc715915 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -76,9 +76,7 @@ chip soc/intel/tigerlake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on # SA Thermal Device - register "Device4Enable" = "1" - end + device pci 04.0 on end # SA Thermal Device device pci 05.0 off end # IPU device pci 06.0 off end # PEG60 device pci 07.0 on end # TBT_PCIe0 diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index 7a3e072236..dc369adc8e 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -105,9 +105,7 @@ chip soc/intel/tigerlake register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref peg on # PCIe PEG0 x4, Clock 0 (SSD1) register "PcieClkSrcUsage[0]" = "0x40" diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index aabeedbf6b..3764d07658 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -105,9 +105,7 @@ chip soc/intel/tigerlake register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref peg on # PCIe PEG0 x4, Clock 0 (SSD1) register "PcieClkSrcUsage[0]" = "0x40" diff --git a/src/mainboard/system76/gaze16/devicetree.cb b/src/mainboard/system76/gaze16/devicetree.cb index f5f216cc4b..8b43202860 100644 --- a/src/mainboard/system76/gaze16/devicetree.cb +++ b/src/mainboard/system76/gaze16/devicetree.cb @@ -96,9 +96,7 @@ chip soc/intel/tigerlake register "DdiPortBHpd" = "1" register "DdiPortBDdc" = "1" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref gna on end device ref north_xhci on # TODO: No TBT, but needed for USB 2.0 on Type-C port? diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index 2c03e60d81..21928ec089 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -105,9 +105,7 @@ chip soc/intel/tigerlake register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref peg on # PCIe PEG0 x4, Clock 3 (SSD1) # Despite the name, SSD2_CLKREQ# is used for SSD1 diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb index 4263806b34..e6372fd8ab 100644 --- a/src/mainboard/system76/oryp8/devicetree.cb +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -110,9 +110,7 @@ chip soc/intel/tigerlake register "DdiPortAHpd" = "1" register "DdiPortADdc" = "0" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref peg0 on # PCIe PEG0 x4, Clock 7 (SSD1) register "PcieClkSrcUsage[7]" = "0x40" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 09c8db1caf..fb0d8278b8 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -274,8 +274,6 @@ struct soc_intel_tigerlake_config { /* Gfx related */ uint8_t SkipExtGfxScan; - uint8_t Device4Enable; - /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 89c8126af0..40676f1b7d 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -474,7 +474,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SlowSlewRate[0] = config->SlowSlewRate; /* Enable TCPU for processor thermal control */ - params->Device4Enable = config->Device4Enable; + params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); /* Set TccActivationOffset */ params->TccActivationOffset = config->tcc_offset; |