diff options
| -rw-r--r-- | src/mainboard/prodrive/hermes/devicetree.cb | 7 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.c | 15 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chipset_pch_h.cb | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/uart/chip.h | 15 | ||||
| -rw-r--r-- | src/soc/intel/common/block/uart/uart.c | 14 |
5 files changed, 17 insertions, 38 deletions
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index ea9f6731f7..ee73800c40 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -170,12 +170,7 @@ chip soc/intel/cannonlake # This device does not have any function on CNP-H, but it needs # to be here so that the resource allocator is aware of UART 2. device ref i2c4 hidden end - device ref uart2 hidden # in ACPI mode - chip soc/intel/common/block/uart - register "devid" = "PCI_DID_INTEL_CNP_H_UART2" - device generic 0 hidden end - end - end + device ref uart2 hidden end # in ACPI mode device ref pcie_rp21 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" register "PcieRpEnable[20]" = "1" diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index bda66bd1dd..e2e4a6bda5 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <device/pci.h> +#include <device/pci_ids.h> #include <fsp/api.h> #include <fsp/util.h> #include <gpio.h> @@ -153,10 +154,20 @@ void soc_init_pre_device(void *chip_info) soc_gpio_pm_configuration(); /* swap enabled PCI ports in device tree if needed */ - if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) + if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) { pcie_rp_update_devicetree(pch_h_rp_groups); - else + + /* + * Fix up device ID of hidden PCI device in devicetree. + * This is used by soc/intel/common/block/uart.c to generate ACPI + */ + struct device *uart2 = PCH_DEV_UART2; + if (uart2->hidden) + uart2->device = PCI_DID_INTEL_CNP_H_UART2; + + } else { pcie_rp_update_devicetree(pch_lp_rp_groups); + } } static void cpu_fill_ssdt(const struct device *dev) diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb index 022e31f67d..77c0d84351 100644 --- a/src/soc/intel/cannonlake/chipset_pch_h.cb +++ b/src/soc/intel/cannonlake/chipset_pch_h.cb @@ -92,7 +92,9 @@ chip soc/intel/cannonlake device pci 17.0 alias sata off end # SATA device pci 19.0 alias i2c4 off end # I2C #4 device pci 19.1 alias i2c5 off end # I2C #5 - device pci 19.2 alias uart2 off end # UART #2 + device pci 19.2 alias uart2 off # UART #2 + ops uart_ops + end device pci 1a.0 alias emmc off end # eMMC device pci 1b.0 alias pcie_rp17 off end # PCI Express Port 17 device pci 1b.1 alias pcie_rp18 off end # PCI Express Port 18 diff --git a/src/soc/intel/common/block/uart/chip.h b/src/soc/intel/common/block/uart/chip.h deleted file mode 100644 index 5981126fa9..0000000000 --- a/src/soc/intel/common/block/uart/chip.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -/* Indirect include for static.c: */ -#include <device/pci_ids.h> - -#ifndef _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_ -#define _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_ - -struct soc_intel_common_block_uart_config { - /* The Device ID read from config space at offset[2:4] when not hidden */ - u16 devid; -}; - -#endif /* _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_ */ diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index e52bb0f62e..e454f7e91a 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -14,7 +14,6 @@ #include <soc/pci_devs.h> #include <soc/iomap.h> #include <soc/nvs.h> -#include "chip.h" #define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) @@ -430,17 +429,4 @@ static const struct pci_driver pch_uart __pci_driver = { .vendor = PCI_VID_INTEL, .devices = pci_device_ids, }; - -static void uart_enable(struct device *dev) -{ - struct soc_intel_common_block_uart_config *conf = dev->chip_info; - dev->ops = &uart_ops; - dev->device = conf ? conf->devid : 0; -} - -struct chip_operations soc_intel_common_block_uart_ops = { - .name = "LPSS UART in ACPI mode", - .enable_dev = uart_enable -}; - #endif /* ENV_RAMSTAGE */ |