diff options
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/lpss.h | 30 | ||||
| -rw-r--r-- | src/soc/intel/common/block/lpss/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/lpss/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/intel/common/block/lpss/lpss.c | 60 |
4 files changed, 97 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h new file mode 100644 index 0000000000..03a47144c8 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_LPSS_H +#define SOC_INTEL_COMMON_BLOCK_LPSS_H + +#include <stdint.h> + +/* Gets controller out of reset */ +void lpss_reset_release(uintptr_t base); + +/* + * Update clock divider parameters. Clock frequency is + * configured as SOC_INTEL_COMMON_LPSS_CLOCK_MHZ * (M / N) + */ +void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val); + +#endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */ diff --git a/src/soc/intel/common/block/lpss/Kconfig b/src/soc/intel/common/block/lpss/Kconfig new file mode 100644 index 0000000000..f8ce731ecb --- /dev/null +++ b/src/soc/intel/common/block/lpss/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_LPSS + bool + help + Intel Processor common LPSS support diff --git a/src/soc/intel/common/block/lpss/Makefile.inc b/src/soc/intel/common/block/lpss/Makefile.inc new file mode 100644 index 0000000000..6c56c6831e --- /dev/null +++ b/src/soc/intel/common/block/lpss/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c +verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
\ No newline at end of file diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c new file mode 100644 index 0000000000..146fdab2ed --- /dev/null +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <intelblocks/lpss.h> + +/* Clock register */ +#define LPSS_CLOCK_CTL_REG 0x200 +#define LPSS_CNT_CLOCK_EN 1 +#define LPSS_CNT_CLK_UPDATE (1 << 31) +#define LPSS_CLOCK_DIV_N(n) (((n) & 0x7fff) << 16) +#define LPSS_CLOCK_DIV_M(m) (((m) & 0x7fff) << 1) + +/* reset register */ +#define LPSS_RESET_CTL_REG 0x204 + +/* + * Bit 1:0 controls LPSS controller reset. + * + * 00 ->LPSS Host Controller is in reset (Reset Asserted) + * 01/10 ->Reserved + * 11 ->LPSS Host Controller is NOT at reset (Reset Released) + */ + +#define LPSS_CNT_RST_RELEASE 3 + +/* DMA Software Reset Control */ +#define LPSS_DMA_RST_RELEASE (1 << 2) + +void lpss_reset_release(uintptr_t base) +{ + uint8_t *addr = (void *)base; + + /* Take controller out of reset */ + write32(addr + LPSS_RESET_CTL_REG, LPSS_CNT_RST_RELEASE); +} + +void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val) +{ + uint8_t *addr = (void *)base; + uint32_t clk_sel; + + addr += LPSS_CLOCK_CTL_REG; + clk_sel = LPSS_CLOCK_DIV_N(clk_n_val) | LPSS_CLOCK_DIV_M(clk_m_val); + + write32(addr, clk_sel | LPSS_CNT_CLK_UPDATE); + write32(addr, clk_sel | LPSS_CNT_CLOCK_EN); +} |