diff options
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 13 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 10 |
2 files changed, 21 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3c8a68baf1..b8dfafde46 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -64,6 +64,19 @@ struct soc_intel_cannonlake_config { /* Enable DPTF support */ int dptf_enable; + enum { + MAX_PC_DEFAULT = 0, + MAX_PC0_1 = 1, + MAX_PC2 = 2, + MAX_PC3 = 3, + MAX_PC6 = 4, + MAX_PC7 = 5, + MAX_PC7S = 6, + MAX_PC8 = 7, + MAX_PC9 = 8, + MAX_PC10 = 9, + } max_package_c_state; + /* Deep SX enable for both AC and DC */ int deep_s3_enable_ac; int deep_s3_enable_dc; diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 5b39156292..69ab1d54c5 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -55,10 +55,16 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void configure_c_states(void) +static void configure_c_states(const config_t *const cfg) { msr_t msr; + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); + if (cfg->max_package_c_state && (msr.lo & 0xf) >= cfg->max_package_c_state) { + msr.lo = (msr.lo & ~0xf) | ((cfg->max_package_c_state - 1) & 0xf); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); + } + /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */ msr.hi = 0; msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; @@ -104,7 +110,7 @@ void soc_core_init(struct device *cpu) setup_lapic(); /* Configure c-state interrupt response time */ - configure_c_states(); + configure_c_states(cfg); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); |