diff options
| -rw-r--r-- | src/arch/x86/Kconfig | 17 | ||||
| -rw-r--r-- | src/lib/cbfs.c | 8 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index b0e479b1c4..90ece988c0 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -160,6 +160,23 @@ config PRERAM_CBFS_CACHE_SIZE Define the size of the Pre-RAM stages CBFS cache. A size of zero disables the CBFS cache feature in pre-memory stages. +config POSTRAM_CBFS_CACHE_IN_BSS + bool + default y if !SOC_AMD_COMMON_BLOCK_NONCAR + help + Allocate the post-memory CBFS cache scratchpad in the .bss + section. CBFS cache will rely on a simple static C buffer + while traditionally CBFS cache memory region is reserved in + the device memory layout. + +config RAMSTAGE_CBFS_CACHE_SIZE + hex + default 0x4000 + depends on POSTRAM_CBFS_CACHE_IN_BSS + help + Define the size of the ramstage CBFS cache. A size of zero + disables the CBFS cache feature in ramstage. + config PC80_SYSTEM bool default y if ARCH_X86 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 8c3db4bd91..1663517921 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -20,8 +20,16 @@ #include <thread.h> #include <timestamp.h> +#if ENV_X86 && (ENV_POSTCAR || ENV_SMM) +struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0, 0); +#elif CONFIG(POSTRAM_CBFS_CACHE_IN_BSS) && ENV_RAMSTAGE +static u8 cache_buffer[CONFIG_RAMSTAGE_CBFS_CACHE_SIZE]; +struct mem_pool cbfs_cache = + MEM_POOL_INIT(cache_buffer, sizeof(cache_buffer), CONFIG_CBFS_CACHE_ALIGN); +#else struct mem_pool cbfs_cache = MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache), CONFIG_CBFS_CACHE_ALIGN); +#endif static void switch_to_postram_cache(int unused) { |