diff options
34 files changed, 483 insertions, 483 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 9bffafdb76..f676c5f43e 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -112,11 +112,11 @@ chip soc/intel/skylake # make boards with better PCHs, which can have up to six SATA ports. # However, the H110 PCH only has four SATA ports, which explains why # two connectors are missing. - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, }" end device pci 19.0 off end # UART #2 diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index a4a090674e..cb3df2ee32 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -38,15 +38,15 @@ chip soc/intel/skylake register "SaGv" = "SaGv_Enabled" register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 0, \ - [2] = 0, \ - [3] = 0, \ - [4] = 0, \ - [5] = 0, \ - [6] = 0, \ - [7] = 0, \ + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 0, + [2] = 0, + [3] = 0, + [4] = 0, + [5] = 0, + [6] = 0, + [7] = 0, }" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch @@ -77,55 +77,55 @@ chip soc/intel/skylake #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = VR_CFG_AMP(5.1), \ - .voltage_limit = 1520 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = VR_CFG_AMP(5.1), + .voltage_limit = 1520 }" register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = VR_CFG_AMP(32), \ - .voltage_limit = 1520 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = VR_CFG_AMP(32), + .voltage_limit = 1520 }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = VR_CFG_AMP(35),\ - .voltage_limit = 1520 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520 }" register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = VR_CFG_AMP(31), \ - .voltage_limit = 1520 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520 }" # Send an extra VR mailbox command for the PS4 exit issue @@ -198,18 +198,18 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoDisabled, }" device cpu_cluster 0 on end diff --git a/src/mainboard/google/brya/variants/aurash/overridetree.cb b/src/mainboard/google/brya/variants/aurash/overridetree.cb index bd3e9d1254..2b9ebfea64 100644 --- a/src/mainboard/google/brya/variants/aurash/overridetree.cb +++ b/src/mainboard/google/brya/variants/aurash/overridetree.cb @@ -37,13 +37,13 @@ chip soc/intel/alderlake }" # Type-A port A2 register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(6) | \ - USB_PORT_WAKE_ENABLE(7) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(4) | + USB_PORT_WAKE_ENABLE(6) | + USB_PORT_WAKE_ENABLE(7) | USB_PORT_WAKE_ENABLE(8)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | USB_PORT_WAKE_ENABLE(4)" register "tcc_offset" = "0" # TCC of 100C register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 96e6e60951..fcca3d89f5 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -45,14 +45,14 @@ chip soc/intel/alderlake register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB HUB # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(6) | \ - USB_PORT_WAKE_ENABLE(7) | \ - USB_PORT_WAKE_ENABLE(8) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(6) | + USB_PORT_WAKE_ENABLE(7) | + USB_PORT_WAKE_ENABLE(8) | USB_PORT_WAKE_ENABLE(9)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | USB_PORT_WAKE_ENABLE(4)" register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" # BTB diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index cad69bb95f..e636540033 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -38,13 +38,13 @@ chip soc/intel/alderlake register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(6) | \ - USB_PORT_WAKE_ENABLE(7) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(4) | + USB_PORT_WAKE_ENABLE(6) | + USB_PORT_WAKE_ENABLE(7) | USB_PORT_WAKE_ENABLE(8)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | USB_PORT_WAKE_ENABLE(4)" register "tcc_offset" = "0" # TCC of 100C diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb index 5c3e90c153..ab6fc16408 100644 --- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb @@ -83,13 +83,13 @@ chip soc/intel/jasperlake register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 #Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | USB_PORT_WAKE_ENABLE(4)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | USB_PORT_WAKE_ENABLE(4)" device domain 0 on diff --git a/src/mainboard/google/dedede/variants/dexi/overridetree.cb b/src/mainboard/google/dedede/variants/dexi/overridetree.cb index fc80ba2bdd..2b09088eef 100644 --- a/src/mainboard/google/dedede/variants/dexi/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dexi/overridetree.cb @@ -124,17 +124,17 @@ chip soc/intel/jasperlake register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(4) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(7)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(4) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" device domain 0 on diff --git a/src/mainboard/google/dedede/variants/taranza/overridetree.cb b/src/mainboard/google/dedede/variants/taranza/overridetree.cb index fc80ba2bdd..2b09088eef 100644 --- a/src/mainboard/google/dedede/variants/taranza/overridetree.cb +++ b/src/mainboard/google/dedede/variants/taranza/overridetree.cb @@ -124,17 +124,17 @@ chip soc/intel/jasperlake register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(4) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(7)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(4) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" device domain 0 on diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index e19e2386b2..46069ced39 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -33,15 +33,15 @@ chip soc/intel/skylake #+----------------+-------+-----------------------------------+ # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(4) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(4) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" # GPE configuration diff --git a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb index 92c0d14803..a17f5e0dcf 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb @@ -10,7 +10,7 @@ chip soc/amd/stoneyridge register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "32 * MiB" - register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" device domain 0 on diff --git a/src/mainboard/google/puff/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb index a96cd25244..8b6a9ae1b1 100644 --- a/src/mainboard/google/puff/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/puff/variants/ambassador/overridetree.cb @@ -86,15 +86,15 @@ chip soc/intel/cannonlake register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" # Enable eMMC HS400 diff --git a/src/mainboard/google/puff/variants/dooly/overridetree.cb b/src/mainboard/google/puff/variants/dooly/overridetree.cb index a5cf3baa67..78324ed8af 100644 --- a/src/mainboard/google/puff/variants/dooly/overridetree.cb +++ b/src/mainboard/google/puff/variants/dooly/overridetree.cb @@ -79,9 +79,9 @@ chip soc/intel/cannonlake register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | USB_PORT_WAKE_ENABLE(3)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | USB_PORT_WAKE_ENABLE(2)" # Enable eMMC HS400 diff --git a/src/mainboard/google/puff/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb index 0ccac51019..b1c50a2701 100644 --- a/src/mainboard/google/puff/variants/duffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/duffy/overridetree.cb @@ -147,15 +147,15 @@ chip soc/intel/cannonlake }" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" # Enable eMMC HS400 diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb index 1a6838420a..83f0c166e8 100644 --- a/src/mainboard/google/puff/variants/faffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb @@ -155,15 +155,15 @@ chip soc/intel/cannonlake }" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" # Enable eMMC HS400 diff --git a/src/mainboard/google/puff/variants/genesis/overridetree.cb b/src/mainboard/google/puff/variants/genesis/overridetree.cb index 45eda87332..6458f9f3f5 100644 --- a/src/mainboard/google/puff/variants/genesis/overridetree.cb +++ b/src/mainboard/google/puff/variants/genesis/overridetree.cb @@ -79,15 +79,15 @@ chip soc/intel/cannonlake register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" # Enable eMMC HS400 diff --git a/src/mainboard/google/puff/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb index a2af448b58..6a2dd7b3af 100644 --- a/src/mainboard/google/puff/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/puff/variants/kaisa/overridetree.cb @@ -147,15 +147,15 @@ chip soc/intel/cannonlake }" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" # Enable eMMC HS400 diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb index 3c3b01b925..a89c56dde6 100644 --- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb @@ -79,15 +79,15 @@ chip soc/intel/cannonlake register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" # Enable eMMC HS400 diff --git a/src/mainboard/google/puff/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb index 29f0fa2b9e..91a193977c 100644 --- a/src/mainboard/google/puff/variants/noibat/overridetree.cb +++ b/src/mainboard/google/puff/variants/noibat/overridetree.cb @@ -72,13 +72,13 @@ chip soc/intel/cannonlake register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | USB_PORT_WAKE_ENABLE(5)" # Enable eMMC HS400 diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb index da0001a02b..3cd6a01d21 100644 --- a/src/mainboard/google/puff/variants/puff/overridetree.cb +++ b/src/mainboard/google/puff/variants/puff/overridetree.cb @@ -80,15 +80,15 @@ chip soc/intel/cannonlake register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(4) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" # Enable eMMC HS400 diff --git a/src/mainboard/google/puff/variants/scout/overridetree.cb b/src/mainboard/google/puff/variants/scout/overridetree.cb index 324f9fbac8..5462e9b700 100644 --- a/src/mainboard/google/puff/variants/scout/overridetree.cb +++ b/src/mainboard/google/puff/variants/scout/overridetree.cb @@ -86,15 +86,15 @@ chip soc/intel/cannonlake register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" # Enable eMMC HS400 diff --git a/src/mainboard/google/puff/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb index 0aac160cc7..60ba0bcf51 100644 --- a/src/mainboard/google/puff/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/puff/variants/wyvern/overridetree.cb @@ -83,13 +83,13 @@ chip soc/intel/cannonlake register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | USB_PORT_WAKE_ENABLE(5)" # Enable eMMC HS400 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 14df721320..93ec7cf9ca 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -131,13 +131,13 @@ chip soc/intel/cannonlake register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera register "usb2_ports[6]" = "{ - .enable = 1, \ - .ocpin = OC_SKIP, \ - .tx_bias = USB2_BIAS_0MV, \ - .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ - .pre_emp_bias = USB2_BIAS_28P15MV, \ - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ - }" # WWAN + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index bf1b235914..b015fc641c 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -55,55 +55,55 @@ chip soc/intel/skylake #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(4), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = VR_CFG_AMP(7), \ - .voltage_limit = 1520 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520 }" register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = VR_CFG_AMP(34), \ - .voltage_limit = 1520 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520 }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = VR_CFG_AMP(35),\ - .voltage_limit = 1520 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520 }" register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = VR_CFG_AMP(35), \ - .voltage_limit = 1520 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520 }" # Send an extra VR mailbox command for the PS4 exit issue diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index d512814023..f1ad6a2385 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -73,28 +73,28 @@ chip soc/intel/skylake register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 1, \ - [5] = 1, \ - [6] = 1, \ - [7] = 1, \ + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, }" - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" # PL2 override 60W diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 2c93a38921..27652d0fe5 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -24,16 +24,16 @@ chip soc/intel/skylake #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = VR_CFG_AMP(7), \ - .voltage_limit = 1520 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520 }" # Enable Root ports. @@ -96,18 +96,18 @@ chip soc/intel/skylake register "SsicPortEnable" = "1" # Enable SSIC for WWAN # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoPci, \ - [PchSerialIoIndexI2C3] = PchSerialIoPci, \ - [PchSerialIoIndexI2C4] = PchSerialIoPci, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" device domain 0 on diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 23cbf96f40..3a75b486be 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -29,55 +29,55 @@ chip soc/intel/skylake #* VrVoltageLimit command not sent. register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = 0, \ - .voltage_limit = 0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, + .voltage_limit = 0 }" register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = 0, \ - .voltage_limit = 0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, + .voltage_limit = 0 }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = 0 ,\ - .voltage_limit = 0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, + .voltage_limit = 0 }" register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = 0, \ - .voltage_limit = 0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, + .voltage_limit = 0 }" # Enable Root ports. @@ -133,18 +133,18 @@ chip soc/intel/skylake register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoPci, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" # Use default SD card detect GPIO configuration diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 869539647a..6d51f440c0 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -26,55 +26,55 @@ chip soc/intel/skylake #* VrVoltageLimit command not sent. register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(4), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = 0, \ - .voltage_limit = 0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, + .voltage_limit = 0 }" register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = 0, \ - .voltage_limit = 0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, + .voltage_limit = 0 }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = 0 ,\ - .voltage_limit = 0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, + .voltage_limit = 0 }" register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0, \ - .imon_offset = 0, \ - .icc_max = 0, \ - .voltage_limit = 0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, + .voltage_limit = 0 }" # Enable Root port. @@ -124,30 +124,30 @@ chip soc/intel/skylake register "SsicPortEnable" = "1" # Enable SSIC for WWAN register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 1, \ - [5] = 1, \ - [6] = 1, \ - [7] = 1, \ + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, }" # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" # PL2 override 25W diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index bc068c6d69..03ace202f6 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -132,18 +132,18 @@ chip soc/intel/skylake register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoPci, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" # PL2 override 25W diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index fcd99ac610..c344819225 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -157,28 +157,28 @@ chip soc/intel/skylake # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 1, \ - [5] = 1, \ - [6] = 1, \ - [7] = 1, \ + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, }" - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoPci, \ - [PchSerialIoIndexI2C3] = PchSerialIoPci, \ - [PchSerialIoIndexI2C4] = PchSerialIoPci, \ - [PchSerialIoIndexI2C5] = PchSerialIoPci, \ - [PchSerialIoIndexSpi0] = PchSerialIoPci, \ - [PchSerialIoIndexSpi1] = PchSerialIoPci, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoPci, \ - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSpi0] = PchSerialIoPci, + [PchSerialIoIndexSpi1] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoPci, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" # PL2 override 25W diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb index 734f3f3842..953c8191f4 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -89,11 +89,11 @@ chip soc/intel/apollolake end # LPC device pci 1f.1 on # SMBUS chip drivers/i2c/nct7802y # Hardware Monitor - register "sensors" = "{ \ - .local_enable = 1, \ - .rtd[2] = RTD_VOLTAGE_MODE, \ - .rtd[1] = RTD_VOLTAGE_MODE, \ - .rtd[0] = RTD_THERMISTOR_MODE, \ + register "sensors" = "{ + .local_enable = 1, + .rtd[2] = RTD_VOLTAGE_MODE, + .rtd[1] = RTD_VOLTAGE_MODE, + .rtd[0] = RTD_THERMISTOR_MODE, }" # FAN0 register "fan[0].mode" = "FAN_SMART" diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 3ba2b0198d..dd04aa9836 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -89,19 +89,19 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" # USB related - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6) | \ - USB_PORT_WAKE_ENABLE(7) | \ - USB_PORT_WAKE_ENABLE(8) | \ + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(4) | + USB_PORT_WAKE_ENABLE(5) | + USB_PORT_WAKE_ENABLE(6) | + USB_PORT_WAKE_ENABLE(7) | + USB_PORT_WAKE_ENABLE(8) | USB_PORT_WAKE_ENABLE(9)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | USB_PORT_WAKE_ENABLE(4)" register "PchUsb2PhySusPgDisable" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 1f17fb1358..157bbbfae3 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -175,18 +175,18 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoDisabled, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoDisabled, }" device cpu_cluster 0 on end diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 1365d85126..9e6d4fbd81 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -152,18 +152,18 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoDisabled, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoDisabled, }" device cpu_cluster 0 on end diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 76f75800b3..d98c20ed57 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -5,15 +5,15 @@ chip soc/intel/skylake # SATA configuration register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 1, \ - [5] = 1, \ - [6] = 1, \ - [7] = 1, \ + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, }" # LPC |