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-rw-r--r--src/soc/nvidia/tegra124/spi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c
index 3a078f8573..4e0285de5b 100644
--- a/src/soc/nvidia/tegra124/spi.c
+++ b/src/soc/nvidia/tegra124/spi.c
@@ -605,7 +605,7 @@ static int xfer_setup(struct tegra_spi_channel *spi, void *buf,
* When we enable caching we'll need to clean/invalidate portions of
* memory. So we need to be careful about memory alignment. Also, DMA
* likes to operate on 4-bytes at a time on the AHB side. So for
- * example, if we only want to receive 1 byte, 4 bytes will be be
+ * example, if we only want to receive 1 byte, 4 bytes will be
* written in memory even if those extra 3 bytes are beyond the length
* we want.
*