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-rw-r--r--src/cpu/amd/car/cache_as_ram.inc8
-rw-r--r--src/cpu/amd/microcode/microcode.c3
-rw-r--r--src/include/cpu/amd/msr.h2
3 files changed, 8 insertions, 5 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 7cbf1dbcbb..e4c2704727 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -415,26 +415,26 @@ fam10_mtrr_setup_complete:
jmp_if_not_fam15h(fam15_car_msr_setup_complete)
/* Disable streaming store (DisSS = 1) */
- mov $0xc0011020, %ecx
+ mov $LS_CFG_MSR, %ecx
rdmsr
bts $28, %eax
wrmsr
/* Disable speculative ITLB reloads (DisSpecTlbRld = 1) */
- mov $0xc0011021, %ecx
+ mov $IC_CFG_MSR, %ecx
rdmsr
bts $9, %eax
wrmsr
/* Disable speculative DTLB reloads (DisSpecTlbRld = 1) and set DisHwPf = 1 */
- mov $0xc0011022, %ecx
+ mov $DC_CFG_MSR, %ecx
rdmsr
bts $4, %eax
bts $13, %eax
wrmsr
/* Disable CR0 combining (CombineCr0Cd = 0) */
- mov $0xc001102b, %ecx
+ mov $BU_CFG3_MSR, %ecx
rdmsr
btr $49-32, %edx
wrmsr
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 68b6953be8..29a550d529 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -17,6 +17,7 @@
#include <stdint.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
#include <cpu/amd/microcode.h>
#include <cbfs.h>
#include <arch/io.h>
@@ -121,7 +122,7 @@ static void apply_microcode_patch(const struct microcode *m)
msr.hi = 0;
msr.lo = (uint32_t)m;
- wrmsr(0xc0010020, msr);
+ wrmsr(MSR_PATCH_LOADER, msr);
UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index 46ec70d3c9..5d7b5e4fda 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -58,6 +58,8 @@
#define PSTATE_3_MSR 0xC0010067
#define PSTATE_4_MSR 0xC0010068
+#define MSR_PATCH_LOADER 0xC0010020
+
#define MSR_COFVID_STS 0xC0010071
#define MSR_CSTATE_ADDRESS 0xC0010073
#define OSVW_ID_Length 0xC0010140