diff options
| -rw-r--r-- | src/soc/mediatek/common/include/soc/pll_common.h | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8195/pll.c | 6 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8195/usb.c | 3 |
3 files changed, 8 insertions, 2 deletions
diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 2ebb71aa2e..6eac8b282a 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -72,6 +72,7 @@ void mt_pll_raise_little_cpu_freq(u32 freq); void mt_pll_raise_cci_freq(u32 freq); void mt_pll_set_tvd_pll1_freq(u32 freq); void edp_mux_set_sel(u32 sel); +void mt_pll_set_usb_clock(void); enum fmeter_type { FMETER_ABIST = 0, diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index 046008cbd6..06b2156702 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -893,3 +893,9 @@ u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) return 0; } + +void mt_pll_set_usb_clock(void) +{ + setbits32(&mtk_topckgen->clk_cfg_11_clr, BIT(7) | BIT(15)); + setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(1) | BIT(31)); +} diff --git a/src/soc/mediatek/mt8195/usb.c b/src/soc/mediatek/mt8195/usb.c index b3f00a97cc..7b893d9e0a 100644 --- a/src/soc/mediatek/mt8195/usb.c +++ b/src/soc/mediatek/mt8195/usb.c @@ -7,8 +7,7 @@ void mtk_usb_prepare(void) { - setbits32(&mtk_topckgen->clk_cfg_11_clr, BIT(7) | BIT(15)); - setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(1) | BIT(31)); + mt_pll_set_usb_clock(); } void mtk_usb_adjust_phy_shift(void) |