diff options
| -rw-r--r-- | src/mainboard/thomson/ip1000/Config.lb | 145 | ||||
| -rw-r--r-- | src/mainboard/thomson/ip1000/Options.lb | 95 | ||||
| -rwxr-xr-x | src/mainboard/thomson/ip1000/auto.c | 126 | ||||
| -rw-r--r-- | src/mainboard/thomson/ip1000/chip.h | 25 | ||||
| -rw-r--r-- | src/mainboard/thomson/ip1000/gpio.c | 120 | ||||
| -rw-r--r-- | src/mainboard/thomson/ip1000/irq_tables.c | 50 | ||||
| -rw-r--r-- | src/mainboard/thomson/ip1000/mainboard.c | 26 | ||||
| -rw-r--r-- | src/mainboard/thomson/ip1000/spd_table.h | 40 | ||||
| -rw-r--r-- | targets/thomson/ip1000/Config-abuild.lb | 30 | ||||
| -rw-r--r-- | targets/thomson/ip1000/Config.lb | 63 |
10 files changed, 720 insertions, 0 deletions
diff --git a/src/mainboard/thomson/ip1000/Config.lb b/src/mainboard/thomson/ip1000/Config.lb new file mode 100644 index 0000000000..9405695608 --- /dev/null +++ b/src/mainboard/thomson/ip1000/Config.lb @@ -0,0 +1,145 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 65536 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE object irq_tables.o end +# object reset.o +if HAVE_ACPI_TABLES + object fadt.o + object dsdt.o + object acpi_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc +dir /pc80 +config chip.h + +chip northbridge/intel/i82830 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + chip drivers/pci/onboard # Onboard VGA + device pci 2.0 on end # VGA (Intel 82830 CGC) + register "rom_address" = "0xfff00000" + end + chip southbridge/intel/i82801xx # Southbridge + device pci 1d.0 on end # USB UHCI Controller #1 + device pci 1d.1 on end # USB UHCI Controller #2 + device pci 1d.2 on end # USB UHCI Controller #3 + device pci 1d.7 on end # USB2 EHCI Controller + device pci 1e.0 on # PCI bridge + device pci 08.0 on end # Intel 82801DB PRO/100 VE Ethernet + end + device pci 1f.0 on # ISA/LPC bridge + chip superio/smsc/smscsuperio # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # Com2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard interrupt + irq 0x72 = 12 # Mouse interrupt + end + device pnp 2e.9 off end # Game port + device pnp 2e.a on # PME + io 0x60 = 0x800 + end + device pnp 2e.b off end # MPU-401 + end + end + device pci 1f.1 on end # IDE + device pci 1f.3 on end # SMBus + device pci 1f.5 on end # AC'97 audio + device pci 1f.6 off end # AC'97 modem + end + end + device apic_cluster 0 on # APIC cluster + chip cpu/intel/socket_PGA370 # Low Voltage PIII Micro-FCBGA Socket 479 + device apic 0 on end # APIC + end + end +end + diff --git a/src/mainboard/thomson/ip1000/Options.lb b/src/mainboard/thomson/ip1000/Options.lb new file mode 100644 index 0000000000..bda1fbc5e5 --- /dev/null +++ b/src/mainboard/thomson/ip1000/Options.lb @@ -0,0 +1,95 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses CC +uses CONFIG_CONSOLE_SERIAL8250 +uses CONFIG_CONSOLE_VGA +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_IOAPIC +uses CONFIG_PCI_ROM_RUN +uses CONFIG_ROM_PAYLOAD +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_UDELAY_TSC +uses CONFIG_VIDEO_MB +uses CROSS_COMPILE +uses DEFAULT_CONSOLE_LOGLEVEL +uses FALLBACK_SIZE +uses HAVE_ACPI_TABLES +uses HAVE_FALLBACK_BOOT +uses HAVE_MP_TABLE +uses HAVE_OPTION_TABLE +uses HAVE_PIRQ_TABLE +uses HEAP_SIZE +uses HOSTCC +uses IRQ_SLOT_COUNT +uses COREBOOT_EXTRA_VERSION +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses MAXIMUM_CONSOLE_LOGLEVEL +uses OBJCOPY +uses PAYLOAD_SIZE +uses _RAMBASE +uses _ROMBASE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses ROM_SIZE +uses STACK_SIZE +uses TTYS0_BASE +uses TTYS0_BAUD +uses TTYS0_LCS +uses USE_FALLBACK_IMAGE +uses USE_OPTION_TABLE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE + +default ROM_SIZE = 512 * 1024 +default ROM_IMAGE_SIZE = 128 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default FALLBACK_SIZE = 256 * 1024 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 7 +default HAVE_MP_TABLE = 0 +default HAVE_ACPI_TABLES = 0 +default CONFIG_IOAPIC = 0 +default HAVE_OPTION_TABLE = 0 +default CONFIG_CONSOLE_VGA = 0 +default CONFIG_PCI_ROM_RUN = 0 +default CONFIG_VIDEO_MB = 0 +default STACK_SIZE = 0x2000 +default HEAP_SIZE = 0x4000 +default _RAMBASE = 0x00004000 +default USE_OPTION_TABLE = 0 +default CONFIG_ROM_PAYLOAD = 1 +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default MAINBOARD_VENDOR = "THOMSON" +default MAINBOARD_PART_NUMBER = "IP1000" +end diff --git a/src/mainboard/thomson/ip1000/auto.c b/src/mainboard/thomson/ip1000/auto.c new file mode 100755 index 0000000000..205d11b63e --- /dev/null +++ b/src/mainboard/thomson/ip1000/auto.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "pc80/udelay_io.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" +#include "northbridge/intel/i82830/raminit.h" +#include "northbridge/intel/i82830/memory_initialized.c" +#include "southbridge/intel/i82801xx/i82801xx.h" +#include "southbridge/intel/i82801xx/i82801xx_reset.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "spd_table.h" +#include "gpio.c" + +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + +#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c" + +/** + * The onboard 64MB PC133 memory does not have a SPD EEPROM so the + * values have to be set manually, the SO-DIMM socket is located in + * socket0 (0x50), and the onboard memory is located in socket1 (0x51). + */ +static inline int spd_read_byte(unsigned device, unsigned address) +{ + int i; + + if (device == 0x50) { + return smbus_read_byte(device, address); + } else if (device == 0x51) { + for (i = 0; i < ARRAY_SIZE(spd_table); i++) { + if (spd_table[i].address == address) + return spd_table[i].data; + } + return 0xFF; /* Return 0xFF when address is not found. */ + } else { + return 0xFF; /* Return 0xFF on any failures. */ + } +} + +#include "northbridge/intel/i82830/raminit.c" +#include "sdram/generic_sdram.c" + +/** + * The AC'97 Audio Controller I/O space registers are read only by default + * so we need to enable them by setting register 0x41 to 0x01. + */ +static void ac97_io_enable(void) +{ + device_t dev; + + /* Set the ac97 audio device staticly. */ + dev = PCI_DEV(0x0, 0x1f, 0x5); + + /* Enable access to the IO space. */ + pci_write_config8(dev, 0x41, 0x01); +} + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .channel0 = {0x50, 0x51}, + } + }; + + if (bist == 0) + early_mtrr_init(); + if (memory_initialized()) { + hard_reset(); + } + + enable_smbus(); + + smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + mb_gpio_init(); + uart_init(); + console_init(); + + /* Prevent the TCO timer from rebooting us */ + i82801xx_halt_tco_timer(); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + sdram_set_registers(memctrl); + sdram_set_spd_registers(memctrl); + sdram_enable(0, memctrl); + + /* Check RAM. */ + /* ram_check(0, 640 * 1024); */ + /* ram_check(64512 * 1024, 65536 * 1024); */ + + ac97_io_enable(); +} diff --git a/src/mainboard/thomson/ip1000/chip.h b/src/mainboard/thomson/ip1000/chip.h new file mode 100644 index 0000000000..f01bfb6d47 --- /dev/null +++ b/src/mainboard/thomson/ip1000/chip.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_thomson_ip1000_ops; + +struct mainboard_thomson_ip1000_config { + int nothing; +}; diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c new file mode 100644 index 0000000000..091db971c7 --- /dev/null +++ b/src/mainboard/thomson/ip1000/gpio.c @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define PME_DEV PNP_DEV(0x2e, 0x0a) +#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */ +#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */ + +/* Early mainboard specific GPIO setup. */ +static void mb_gpio_init(void) +{ + device_t dev; + uint16_t port; + uint32_t set_gpio; + + /* Southbridge GPIOs. */ + /* Set the LPC device statically. */ + dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); + + /* Set GPIO25 to input and drive GPIO23 to high, + * this enables the LAN controller. + */ + udelay(10); + set_gpio = 0x0000ffff; + set_gpio |= 1 << 25; + outl(set_gpio, ICH_IO_BASE_ADDR + 0x04); + + set_gpio = 0x1b3f0000; + set_gpio |= 1 << 23; + outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c); + + /* Super I/O GPIOs. */ + dev = PME_DEV; + port = dev >> 8; + + outb(0x55, port); /* Enter the configuration state. */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR); + pnp_set_enable(dev, 1); + outl(0x03, PME_IO_BASE_ADDR + 0x1e); /* Force Disk Change */ + outl(0x02, PME_IO_BASE_ADDR + 0x1f); /* Floppy Data Rate */ + outl(0x81, PME_IO_BASE_ADDR + 0x20); /* UART1 FIFO */ + outl(0x81, PME_IO_BASE_ADDR + 0x21); /* UART2 FIFO */ + outl(0x00, PME_IO_BASE_ADDR + 0x22); /* Device Disable */ + outl(0x01, PME_IO_BASE_ADDR + 0x23); /* GP10 */ + outl(0x01, PME_IO_BASE_ADDR + 0x24); /* GP11 */ + outl(0x01, PME_IO_BASE_ADDR + 0x25); /* GP12 */ + outl(0x01, PME_IO_BASE_ADDR + 0x26); /* GP13 */ + outl(0x01, PME_IO_BASE_ADDR + 0x27); /* GP14 */ + outl(0x01, PME_IO_BASE_ADDR + 0x28); /* GP15 */ + outl(0x01, PME_IO_BASE_ADDR + 0x29); /* GP16 */ + outl(0x01, PME_IO_BASE_ADDR + 0x2a); /* GP17 */ + outl(0x01, PME_IO_BASE_ADDR + 0x2b); /* GP20 */ + outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP21 */ + outl(0x01, PME_IO_BASE_ADDR + 0x2d); /* GP22 */ + outl(0x01, PME_IO_BASE_ADDR + 0x2f); /* GP24 */ + outl(0x01, PME_IO_BASE_ADDR + 0x30); /* GP25 */ + outl(0x01, PME_IO_BASE_ADDR + 0x31); /* GP26 */ + outl(0x01, PME_IO_BASE_ADDR + 0x32); /* GP27 */ + outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP30 */ + outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP31 */ + outl(0x84, PME_IO_BASE_ADDR + 0x35); /* GP32 */ + outl(0x84, PME_IO_BASE_ADDR + 0x36); /* GP33 */ + outl(0x00, PME_IO_BASE_ADDR + 0x37); /* GP34 */ + outl(0x04, PME_IO_BASE_ADDR + 0x38); /* GP35 */ + outl(0x01, PME_IO_BASE_ADDR + 0x39); /* GP36 */ + outl(0x01, PME_IO_BASE_ADDR + 0x3a); /* GP37 */ + outl(0x01, PME_IO_BASE_ADDR + 0x3b); /* GP40 */ + outl(0x01, PME_IO_BASE_ADDR + 0x3c); /* GP41 */ + outl(0x86, PME_IO_BASE_ADDR + 0x3d); /* GP42 */ + outl(0x01, PME_IO_BASE_ADDR + 0x3e); /* GP43 */ + outl(0x05, PME_IO_BASE_ADDR + 0x3f); /* GP50 */ + outl(0x05, PME_IO_BASE_ADDR + 0x40); /* GP51 */ + outl(0x05, PME_IO_BASE_ADDR + 0x41); /* GP52 */ + outl(0x04, PME_IO_BASE_ADDR + 0x42); /* GP53 */ + outl(0x05, PME_IO_BASE_ADDR + 0x43); /* GP54 */ + outl(0x04, PME_IO_BASE_ADDR + 0x44); /* GP55 */ + outl(0x05, PME_IO_BASE_ADDR + 0x45); /* GP56 */ + outl(0x04, PME_IO_BASE_ADDR + 0x46); /* GP57 */ + outl(0x01, PME_IO_BASE_ADDR + 0x47); /* GP58 */ + outl(0x01, PME_IO_BASE_ADDR + 0x48); /* GP59 */ + outl(0x00, PME_IO_BASE_ADDR + 0x4b); /* GP1 */ + outl(0x04, PME_IO_BASE_ADDR + 0x4c); /* GP2 */ + outl(0xc0, PME_IO_BASE_ADDR + 0x4d); /* GP3 */ + outl(0x00, PME_IO_BASE_ADDR + 0x4e); /* GP4 */ + outl(0x04, PME_IO_BASE_ADDR + 0x4f); /* GP5 */ + outl(0x00, PME_IO_BASE_ADDR + 0x50); /* GP6 */ + outl(0x01, PME_IO_BASE_ADDR + 0x56); /* FAN1 */ + outl(0x01, PME_IO_BASE_ADDR + 0x57); /* FAN2 */ + outl(0x58, PME_IO_BASE_ADDR + 0x58); /* Fan Control */ + outl(0xff, PME_IO_BASE_ADDR + 0x59); /* Fan1 Tachometer */ + outl(0x50, PME_IO_BASE_ADDR + 0x5a); /* Fan2 Tachometer */ + outl(0x00, PME_IO_BASE_ADDR + 0x5b); /* Fan1 Preload */ + outl(0x00, PME_IO_BASE_ADDR + 0x5c); /* Fan2 Preload */ + outl(0x00, PME_IO_BASE_ADDR + 0x5d); /* LED1 */ + outl(0x00, PME_IO_BASE_ADDR + 0x5e); /* LED2 */ + outl(0x00, PME_IO_BASE_ADDR + 0x5f); /* Keyboard Scan Code */ + outb(0xaa, port); /* Exit the configuration state. */ +} diff --git a/src/mainboard/thomson/ip1000/irq_tables.c b/src/mainboard/thomson/ip1000/irq_tables.c new file mode 100644 index 0000000000..e6acb60094 --- /dev/null +++ b/src/mainboard/thomson/ip1000/irq_tables.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x24c0, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xcd, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] VGA compatible controller */ + {0x00,(0x1d<<3)|0x0, {{0x60, 0x1ef8}, {0x63, 0x1ef8}, {0x62, 0x1ef8}, {0x6b, 0x01ef8}}, 0x0, 0x0}, /* [D] USB2 EHCI Controller */ + {0x00,(0x1f<<3)|0x0, {{0x62, 0x1ef8}, {0x61, 0x1ef8}, {0x6b, 0x1ef8}, {0x63, 0x01ef8}}, 0x0, 0x0}, /* [A] IDE Controller */ + {0x01,(0x08<<3)|0x0, {{0x68, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] Ethernet controller */ + {0x01,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x01ef8}}, 0x1, 0x0}, /* [A] USB UHCI Controller #1 */ + {0x01,(0x01<<3)|0x0, {{0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x01ef8}}, 0x2, 0x0}, /* [B] USB UHCI Controller #2 */ + {0x01,(0x02<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x01ef8}}, 0x3, 0x0}, /* [C] USB UHCI Controller #3 */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c new file mode 100644 index 0000000000..2a164e8461 --- /dev/null +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_thomson_ip1000_ops = { + CHIP_NAME("THOMSON IP1000 Mainboard") +}; diff --git a/src/mainboard/thomson/ip1000/spd_table.h b/src/mainboard/thomson/ip1000/spd_table.h new file mode 100644 index 0000000000..e771d82014 --- /dev/null +++ b/src/mainboard/thomson/ip1000/spd_table.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <spd.h> + +struct spd_entry { + unsigned int address; + unsigned int data; +}; + +/* + * The onboard 64MB PC133 memory does not have an SPD EEPROM so the values + * have to be set manually, the onboard memory is located in socket1 (0x51). + */ +const struct spd_entry spd_table [] = { + {SPD_MEMORY_TYPE, 0x04}, /* (Fundamental) memory type */ + {SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */ + {SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */ + {SPD_MODULE_DATA_WIDTH_LSB, 0x40}, /* Module data width (LSB) */ + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ + {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ + {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x10}, /* Density of each row on module */ +}; diff --git a/targets/thomson/ip1000/Config-abuild.lb b/targets/thomson/ip1000/Config-abuild.lb new file mode 100644 index 0000000000..8f9ffb80d0 --- /dev/null +++ b/targets/thomson/ip1000/Config-abuild.lb @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target thomson_ip1000 +mainboard thomson/ip1000 + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + payload __PAYLOAD__ +end + +buildrom ./coreboot.rom ROM_SIZE "fallback" + diff --git a/targets/thomson/ip1000/Config.lb b/targets/thomson/ip1000/Config.lb new file mode 100644 index 0000000000..0ee8b7a1e7 --- /dev/null +++ b/targets/thomson/ip1000/Config.lb @@ -0,0 +1,63 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target ip1000 +mainboard thomson/ip1000 + +## +## Total number of bytes allocated for coreboot use +## (fallback images and payloads). +## +# option ROM_SIZE = 1024 * 1024 +## For VGA BIOS (-64k) +option ROM_SIZE = (1024 * 1024) - (64 * 1024) + +## +## VGA Console +## NOTE: to initialize VGA, you need to copy +## the VGA option ROM from the factory BIOS +## 0=disable 1=enable +## +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + +## +## Choose the amount of memory pre-allocated for VGA +## 0 for No memory pre-allocated (Graphics memory Disabled) +## 512 for DVMT (UMA) mode, 512K of memory pre-allocated for frame buffer +## 1 for DVMT (UMA) mode, 1M of memory pre-allocated for frame buffer +## 8 for DVMT (UMA) mode, 8M of memory pre-allocated for frame buffer +## +option CONFIG_VIDEO_MB = 8 + +## +## Request this level of debugging output +## +option DEFAULT_CONSOLE_LOGLEVEL = 7 + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option FALLBACK_SIZE = ROM_SIZE + option COREBOOT_EXTRA_VERSION = "_IP1000" + payload /tmp/filo.elf +# payload /tmp/eb-5.4.3-eepro100.elf +end + +buildrom ./coreboot.rom ROM_SIZE "fallback" |