diff options
| -rw-r--r-- | src/device/pci_class.c | 2 | ||||
| -rw-r--r-- | src/device/pci_rom.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family16kb/state_machine.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctardk4.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/late.c | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/late.c | 4 |
6 files changed, 9 insertions, 9 deletions
diff --git a/src/device/pci_class.c b/src/device/pci_class.c index b2f5ff765c..1326b2c0cc 100644 --- a/src/device/pci_class.c +++ b/src/device/pci_class.c @@ -263,7 +263,7 @@ const char *get_pci_subclass_name(struct device *dev) subclass_name = "???"; class_entry = get_pci_class_entry(dev); subclass_entry = class_entry ? class_entry->subclass_list : NULL; - if (NULL != subclass_entry) { + if (subclass_entry != NULL) { subclass_list_end = &subclass_entry[class_entry->subclass_entries]; while (subclass_list_end > subclass_entry) { diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 65989d4724..82d9a3056a 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -150,7 +150,7 @@ struct rom_header *pci_rom_load(struct device *dev, * whether the ROM image is for a VGA device because some * devices have a mismatch between the hardware and the ROM. */ - if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { + if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) { #if !IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; /* Primary VGA device (device.c). */ if (dev != vga_pri) return NULL; /* Only one VGA supported. */ diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index e6796390bb..9840c1c73c 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -34,7 +34,7 @@ void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) { status = OemInitResume(&Post->MemConfig.MemContext); - if (AGESA_SUCCESS == status) + if (status == AGESA_SUCCESS) Post->MemConfig.MemRestoreCtl = 1; } } diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index f7a4beeeeb..d112c4664b 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -146,6 +146,6 @@ static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, } } p+=10; - } while (0xFF == *p); + } while (*p == 0xff); } } diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 60d40f7049..e3390d5c60 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -353,9 +353,9 @@ static void sb800_enable(struct device *dev) case PCI_DEVFN(0x11, 0): /* 0:11.0 SATA */ if (dev->enabled) { sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; - if (1 == sb_chip->boot_switch_sata_ide) + if (sb_chip->boot_switch_sata_ide == 1) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. - else if (0 == sb_chip->boot_switch_sata_ide) + else if (sb_chip->boot_switch_sata_ide == 0) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; @@ -387,7 +387,7 @@ static void sb800_enable(struct device *dev) case PCI_DEVFN(0x14, 2): /* 0:14:2 HDA */ if (dev->enabled) { - if (AZALIA_DISABLE == sb_config->AzaliaController) { + if (sb_config->AzaliaController == AZALIA_DISABLE) { sb_config->AzaliaController = AZALIA_AUTO; } } else { diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 9a2f837010..25e087f641 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -354,9 +354,9 @@ static void sb900_enable(struct device *dev) case (0x11 << 3) | 0: /* 0:11.0 SATA */ if (dev->enabled) { sb_config->SATAMODE.SataMode.SataController = ENABLED; - if (1 == sb_chip->boot_switch_sata_ide) + if (sb_chip->boot_switch_sata_ide == 1) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. - else if (0 == sb_chip->boot_switch_sata_ide) + else if (sb_chip->boot_switch_sata_ide == 0) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { sb_config->SATAMODE.SataMode.SataController = DISABLED; |