diff options
| -rw-r--r-- | src/soc/amd/common/block/i2c/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/amd/common/block/i2c/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/i2c/i2c.c | 82 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/i2c.h | 36 | ||||
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/picasso/early_fch.c | 23 | ||||
| -rw-r--r-- | src/soc/amd/picasso/i2c.c | 79 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/i2c.h | 7 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/bootblock.c | 26 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/i2c.c | 91 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/i2c.h | 7 |
14 files changed, 177 insertions, 189 deletions
diff --git a/src/soc/amd/common/block/i2c/Kconfig b/src/soc/amd/common/block/i2c/Kconfig new file mode 100644 index 0000000000..5d8498c6af --- /dev/null +++ b/src/soc/amd/common/block/i2c/Kconfig @@ -0,0 +1,4 @@ +config SOC_AMD_COMMON_BLOCK_I2C + bool + help + Select this option to add FCH I2C controller functions to the build. diff --git a/src/soc/amd/common/block/i2c/Makefile.inc b/src/soc/amd/common/block/i2c/Makefile.inc new file mode 100644 index 0000000000..8af77965ce --- /dev/null +++ b/src/soc/amd/common/block/i2c/Makefile.inc @@ -0,0 +1 @@ +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C) += i2c.c diff --git a/src/soc/amd/common/block/i2c/i2c.c b/src/soc/amd/common/block/i2c/i2c.c new file mode 100644 index 0000000000..59e885d807 --- /dev/null +++ b/src/soc/amd/common/block/i2c/i2c.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <delay.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/gpio_banks.h> +#include <amdblocks/gpio_defs.h> +#include <amdblocks/i2c.h> + +#define MAX_PIN_COUNT 4 + +struct common_i2c_save { + uint32_t control_value; + uint8_t mux_value; +}; + +/* + * To program I2C pins without destroying their programming, the registers + * that will be changed need to be saved first. + */ +static void save_i2c_pin_registers(uint8_t gpio, struct common_i2c_save *save_table) +{ + save_table->mux_value = iomux_read8(gpio); + save_table->control_value = gpio_read32(gpio); +} + +static void restore_i2c_pin_registers(uint8_t gpio, struct common_i2c_save *save_table) +{ + /* Write and flush posted writes. */ + iomux_write8(gpio, save_table->mux_value); + iomux_read8(gpio); + gpio_write32(gpio, save_table->control_value); + gpio_read32(gpio); +} + +static void drive_scl(const struct soc_i2c_peripheral_reset_info *reset_info, uint32_t val) +{ + uint8_t j; + + for (j = 0; j < reset_info->num_pins; j++) { + if (reset_info->i2c_scl_reset_mask & reset_info->i2c_scl[j].pin_mask) + gpio_write32(reset_info->i2c_scl[j].pin.gpio, val); + } + + gpio_read32(0); /* Flush posted write */ + /* + * TODO(b/183010197): 4usec gets 85KHz for 1 pin, 70KHz for 4 pins. Ensure this delay + * works fine for all SoCs and make this delay configurable if required. + */ + udelay(4); +} + +void sb_reset_i2c_peripherals(const struct soc_i2c_peripheral_reset_info *reset_info) +{ + struct common_i2c_save save_table[MAX_PIN_COUNT]; + uint8_t i; + + if (!reset_info || !reset_info->i2c_scl || !reset_info->num_pins || + !reset_info->i2c_scl_reset_mask) + return; + + assert(reset_info->num_pins <= MAX_PIN_COUNT); + + /* Save and reprogram I2C SCL pins */ + for (i = 0; i < reset_info->num_pins; i++) { + save_i2c_pin_registers(reset_info->i2c_scl[i].pin.gpio, &save_table[i]); + program_gpios(&reset_info->i2c_scl[i].pin, 1); + } + + /* + * Toggle SCL back and forth 9 times under 100KHz. A single read is + * needed after the writes to force the posted write to complete. + */ + for (i = 0; i < 9; i++) { + drive_scl(reset_info, GPIO_OUTPUT_OUT_HIGH); + drive_scl(reset_info, GPIO_OUTPUT_OUT_LOW); + } + + /* Restore I2C pins. */ + for (i = 0; i < reset_info->num_pins; i++) + restore_i2c_pin_registers(reset_info->i2c_scl[i].pin.gpio, &save_table[i]); +} diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h new file mode 100644 index 0000000000..9fa203bf57 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/i2c.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_COMMON_BLOCK_I2C_H +#define AMD_COMMON_BLOCK_I2C_H + +#include <amdblocks/gpio_banks.h> +#include <types.h> + +/** + * Data structure to identify GPIO to be toggled to reset peripherals on an I2C bus. + * @pin: GPIO corresponding to I2C SCL that needs to be toggled/bit-banged. + * @pin_mask: Bit Mask of a single I2C bus that needs to be reset. + */ +struct soc_i2c_scl_pin { + struct soc_amd_gpio pin; + uint8_t pin_mask; +}; + +/** + * Information about I2C peripherals that need to be reset. + * @i2c_scl_reset_mask: Bit mask of I2C buses that need to be reset based on the device tree + * configuration. + * @i2c_scl: SoC specific I2C SCL pins that need to be bit-banged as part of reset + * procedure. + * @num_pins: Number of pins defined in @i2c_scl. + */ +struct soc_i2c_peripheral_reset_info { + uint8_t i2c_scl_reset_mask; + const struct soc_i2c_scl_pin *i2c_scl; + uint32_t num_pins; +}; + +/* Reset I2C peripherals. */ +void sb_reset_i2c_peripherals(const struct soc_i2c_peripheral_reset_info *reset_info); + +#endif /* AMD_COMMON_BLOCK_I2C_H */ diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index ea9ee5bb3f..1fca390fea 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -34,6 +34,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_HDA + select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 549f03347a..2944b2a46f 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -97,9 +97,9 @@ enum sysinfo_dpphy_override { struct soc_amd_picasso_config { struct soc_amd_common_config common_config; /* - * If sb_reset_i2c_slaves() is called, this devicetree register + * If sb_reset_i2c_peripherals() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. - * For example, should we need I2C0 and I2C3 have their slave + * For example, should we need I2C0 and I2C3 have their peripheral * devices reseted by toggling SCL, use: * * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index a9118adfad..1aff83b5c8 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -2,6 +2,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/espi.h> +#include <amdblocks/i2c.h> #include <amdblocks/lpc.h> #include <amdblocks/smbus.h> #include <amdblocks/spi.h> @@ -11,12 +12,32 @@ #include <soc/uart.h> #include <types.h> +#include "chip.h" + +/* This table is for the initial conversion of all SCL pins to input with no pull. */ +static const struct soc_i2c_scl_pin i2c_scl_pins[] = { + { PAD_GPI(I2C2_SCL_PIN, PULL_NONE), GPIO_I2C2_SCL }, + { PAD_GPI(I2C3_SCL_PIN, PULL_NONE), GPIO_I2C3_SCL }, + /* I2C4 is a peripheral device only */ +}; + static void lpc_configure_decodes(void) { if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)) lpc_enable_port80(); } +static void reset_i2c_peripherals(void) +{ + const struct soc_amd_picasso_config *cfg = config_of_soc(); + struct soc_i2c_peripheral_reset_info reset_info; + + reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK; + reset_info.i2c_scl = i2c_scl_pins; + reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins); + sb_reset_i2c_peripherals(&reset_info); +} + /* Before console init */ void fch_pre_init(void) { @@ -31,7 +52,7 @@ void fch_pre_init(void) fch_enable_cf9_io(); fch_enable_legacy_io(); enable_aoac_devices(); - sb_reset_i2c_slaves(); + reset_i2c_peripherals(); /* * On reset Range_0 defaults to enabled. We want to start with a clean diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index af4c41f8a6..9d016150c0 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -7,6 +7,7 @@ #include <device/device.h> #include <drivers/i2c/designware/dw_i2c.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/i2c.h> #include <soc/i2c.h> #include <soc/iomap.h> #include <soc/pci_devs.h> @@ -141,81 +142,3 @@ struct device_operations picasso_i2c_mmio_ops = { .acpi_name = i2c_acpi_name, .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, }; - -/* - * I2C pins are open drain with external pull up, so in order to bit bang them - * all, SCL pins must become GPIO inputs with no pull, then they need to be - * toggled between input-no-pull and output-low. This table is for the initial - * conversion of all SCL pins to input with no pull. - */ -static const struct soc_amd_gpio i2c_2_gpi[] = { - PAD_GPI(I2C2_SCL_PIN, PULL_NONE), - PAD_GPI(I2C3_SCL_PIN, PULL_NONE), - /* I2C4 is a slave device only */ -}; -#define saved_pins_count ARRAY_SIZE(i2c_2_gpi) - -/* - * To program I2C pins without destroying their programming, the registers - * that will be changed need to be saved first. - */ -static void save_i2c_pin_registers(uint8_t gpio, - struct soc_amd_i2c_save *save_table) -{ - save_table->mux_value = iomux_read8(gpio); - save_table->control_value = gpio_read32(gpio); -} - -static void restore_i2c_pin_registers(uint8_t gpio, - struct soc_amd_i2c_save *save_table) -{ - /* Write and flush posted writes. */ - iomux_write8(gpio, save_table->mux_value); - iomux_read8(gpio); - gpio_write32(gpio, save_table->control_value); - gpio_read32(gpio); -} - -/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ -void sb_reset_i2c_slaves(void) -{ - const struct soc_amd_picasso_config *cfg; - struct soc_amd_i2c_save save_table[saved_pins_count]; - uint8_t i, j, control; - - cfg = config_of_soc(); - control = cfg->i2c_scl_reset & GPIO_I2C_MASK; - if (control == 0) - return; - - /* Save and reprogram I2C SCL pins */ - for (i = 0; i < saved_pins_count; i++) - save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); - program_gpios(i2c_2_gpi, saved_pins_count); - - /* - * Toggle SCL back and forth 9 times under 100KHz. A single read is - * needed after the writes to force the posted write to complete. - */ - for (j = 0; j < 9; j++) { - if (control & GPIO_I2C2_SCL) - gpio_write32(I2C2_SCL_PIN, GPIO_OUTPUT_ENABLE); - if (control & GPIO_I2C3_SCL) - gpio_write32(I2C3_SCL_PIN, GPIO_OUTPUT_ENABLE); - - gpio_read32(0); /* Flush posted write */ - udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */ - - if (control & GPIO_I2C2_SCL) - gpio_write32(I2C2_SCL_PIN, 0); - if (control & GPIO_I2C3_SCL) - gpio_write32(I2C3_SCL_PIN, 0); - - gpio_read32(0); /* Flush posted write */ - udelay(4); - } - - /* Restore I2C pins. */ - for (i = 0; i < saved_pins_count; i++) - restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); -} diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index 41b930b186..f62cb11dc4 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -6,11 +6,6 @@ #include <types.h> #include <soc/gpio.h> -struct soc_amd_i2c_save { - uint32_t control_value; - uint8_t mux_value; -}; - #define GPIO_I2C2_SCL BIT(2) #define GPIO_I2C3_SCL BIT(3) #define GPIO_I2C_MASK (BIT(2) | BIT(3)) @@ -28,8 +23,6 @@ struct soc_amd_i2c_save { #define USB_PD_RFMUX_OVERRIDE BIT(8) #define USB_PD_DP_OVERRIDE BIT(9) -void sb_reset_i2c_slaves(void); - /* Sets the base address for the specific I2C bus. */ void i2c_set_bar(unsigned int bus, uintptr_t bar); diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index dcd6b8f146..5f1b65a476 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_HDA + select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_PCI diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c index 248ee773a4..fc4284f502 100644 --- a/src/soc/amd/stoneyridge/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -12,12 +12,15 @@ #include <amdblocks/agesawrapper_call.h> #include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/biosram.h> +#include <amdblocks/i2c.h> #include <soc/pci_devs.h> #include <soc/cpu.h> #include <soc/southbridge.h> #include <timestamp.h> #include <halt.h> +#include "chip.h" + #if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000 #error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB" #endif @@ -25,6 +28,14 @@ #error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB" #endif +/* This table is for the initial conversion of all SCL pins to input with no pull. */ +static const struct soc_i2c_scl_pin i2c_scl_pins[] = { + { PAD_GPI(I2C0_SCL_PIN, PULL_NONE), GPIO_I2C0_SCL }, + { PAD_GPI(I2C1_SCL_PIN, PULL_NONE), GPIO_I2C1_SCL }, + { PAD_GPI(I2C2_SCL_PIN, PULL_NONE), GPIO_I2C2_SCL }, + { PAD_GPI(I2C3_SCL_PIN, PULL_NONE), GPIO_I2C3_SCL }, +}; + /* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ static void amd_initmmio(void) { @@ -53,6 +64,17 @@ static void amd_initmmio(void) CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE); } +static void reset_i2c_peripherals(void) +{ + const struct soc_amd_stoneyridge_config *cfg = config_of_soc(); + struct soc_i2c_peripheral_reset_info reset_info; + + reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK; + reset_info.i2c_scl = i2c_scl_pins; + reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins); + sb_reset_i2c_peripherals(&reset_info); +} + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { enable_pci_mmconf(); @@ -75,14 +97,14 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) void bootblock_soc_early_init(void) { /* - * This call (sb_reset_i2c_slaves) was originally early at + * This call (sb_reset_i2c_peripherals) was originally early at * bootblock_c_entry, but had to be moved here. There was an * unexplained delay in the middle of the i2c transaction when * we had it in bootblock_c_entry. Moving it to this point * (or adding delays) fixes the issue. It seems like the processor * just pauses but we don't know why. */ - sb_reset_i2c_slaves(); + reset_i2c_peripherals(); bootblock_fch_early_init(); post_code(0x90); } diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 07103a5714..82c54371c5 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -43,9 +43,9 @@ struct soc_amd_stoneyridge_config { size_t uma_size; /* - * If sb_reset_i2c_slaves() is called, this devicetree register + * If sb_reset_i2c_peripherals() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. - * For example, should we need I2C0 and I2C3 have their slave + * For example, should we need I2C0 and I2C3 have their peripheral * devices reseted by toggling SCL, use: * * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 295a833046..7b0bc77e59 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -7,6 +7,7 @@ #include <device/device.h> #include <drivers/i2c/designware/dw_i2c.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/i2c.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> @@ -115,93 +116,3 @@ struct device_operations stoneyridge_i2c_mmio_ops = { .acpi_name = i2c_acpi_name, .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, }; - -/* - * I2C pins are open drain with external pull up, so in order to bit bang them - * all, SCL pins must become GPIO inputs with no pull, then they need to be - * toggled between input-no-pull and output-low. This table is for the initial - * conversion of all SCL pins to input with no pull. - */ -static const struct soc_amd_gpio i2c_2_gpi[] = { - PAD_GPI(I2C0_SCL_PIN, PULL_NONE), - PAD_GPI(I2C1_SCL_PIN, PULL_NONE), - PAD_GPI(I2C2_SCL_PIN, PULL_NONE), - PAD_GPI(I2C3_SCL_PIN, PULL_NONE), -}; -#define saved_pins_count ARRAY_SIZE(i2c_2_gpi) - -/* - * To program I2C pins without destroying their programming, the registers - * that will be changed need to be saved first. - */ -static void save_i2c_pin_registers(uint8_t gpio, - struct soc_amd_i2c_save *save_table) -{ - save_table->mux_value = iomux_read8(gpio); - save_table->control_value = gpio_read32(gpio); -} - -static void restore_i2c_pin_registers(uint8_t gpio, - struct soc_amd_i2c_save *save_table) -{ - /* Write and flush posted writes. */ - iomux_write8(gpio, save_table->mux_value); - iomux_read8(gpio); - gpio_write32(gpio, save_table->control_value); - gpio_read32(gpio); -} - -/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ -void sb_reset_i2c_slaves(void) -{ - const struct soc_amd_stoneyridge_config *cfg; - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - struct soc_amd_i2c_save save_table[saved_pins_count]; - uint8_t i, j, control; - - if (!dev || !dev->chip_info) - return; - cfg = dev->chip_info; - control = cfg->i2c_scl_reset & GPIO_I2C_MASK; - if (control == 0) - return; - - /* Save and reprogram I2C SCL pins */ - for (i = 0; i < saved_pins_count; i++) - save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); - program_gpios(i2c_2_gpi, saved_pins_count); - - /* - * Toggle SCL back and forth 9 times under 100KHz. A single read is - * needed after the writes to force the posted write to complete. - */ - for (j = 0; j < 9; j++) { - if (control & GPIO_I2C0_SCL) - gpio_write32(I2C0_SCL_PIN, GPIO_OUTPUT_ENABLE); - if (control & GPIO_I2C1_SCL) - gpio_write32(I2C1_SCL_PIN, GPIO_OUTPUT_ENABLE); - if (control & GPIO_I2C2_SCL) - gpio_write32(I2C2_SCL_PIN, GPIO_OUTPUT_ENABLE); - if (control & GPIO_I2C3_SCL) - gpio_write32(I2C3_SCL_PIN, GPIO_OUTPUT_ENABLE); - - gpio_read32(0); /* Flush posted write */ - udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */ - - if (control & GPIO_I2C0_SCL) - gpio_write32(I2C0_SCL_PIN, 0); - if (control & GPIO_I2C1_SCL) - gpio_write32(I2C1_SCL_PIN, 0); - if (control & GPIO_I2C2_SCL) - gpio_write32(I2C2_SCL_PIN, 0); - if (control & GPIO_I2C3_SCL) - gpio_write32(I2C3_SCL_PIN, 0); - - gpio_read32(0); /* Flush posted write */ - udelay(4); - } - - /* Restore I2C pins. */ - for (i = 0; i < saved_pins_count; i++) - restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); -} diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h index 0b61329fef..b16084b5ad 100644 --- a/src/soc/amd/stoneyridge/include/soc/i2c.h +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -6,11 +6,6 @@ #include <types.h> #include <soc/gpio.h> -struct soc_amd_i2c_save { - uint32_t control_value; - uint8_t mux_value; -}; - #define GPIO_I2C0_SCL BIT(0) #define GPIO_I2C1_SCL BIT(1) #define GPIO_I2C2_SCL BIT(2) @@ -27,6 +22,4 @@ struct soc_amd_i2c_save { #define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx #define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx -void sb_reset_i2c_slaves(void); - #endif /* AMD_STONEYRIDGE_I2C_H */ |