diff options
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/Makefile.inc | 5 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/state_machine.c | 86 |
2 files changed, 91 insertions, 0 deletions
diff --git a/src/northbridge/amd/pi/00730F01/Makefile.inc b/src/northbridge/amd/pi/00730F01/Makefile.inc index 39c3ee61ba..94cf72e5ad 100644 --- a/src/northbridge/amd/pi/00730F01/Makefile.inc +++ b/src/northbridge/amd/pi/00730F01/Makefile.inc @@ -17,3 +17,8 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c ramstage-y += iommu.c + +ifneq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y) +romstage-y += state_machine.c +ramstage-y += state_machine.c +endif diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c new file mode 100644 index 0000000000..b567f38e2e --- /dev/null +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <cbmem.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + /* If UMA is enabled we currently have it below TOP_MEM as well. + * UMA may or may not be cacheable, so Sub4GCacheTop could be + * higher than UmaBase. With UMA_NONE we see UmaBase==0. */ + if (Post->MemConfig.UmaBase) + backup_top_of_low_cacheable(Post->MemConfig.UmaBase << 16); + else + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + + + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ +} |