diff options
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/iomap.h | 7 |
2 files changed, 8 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 1f0f2feeef..9c5868b0d6 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -208,7 +208,7 @@ config HEAP_SIZE default 0x10000 config GFX_GMA_DEFAULT_MMIO - default 0xfa000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT + default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT # Intel recommends reserving the following resources per PCIe TBT root port, # from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index 94fb5bee09..0c332be2b6 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -88,6 +88,13 @@ #define IOM_BASE_SIZE 0x1600 /* + * If MAINBOARD_HAS_EARLY_LIBGFXINIT is set, the following memory space is used + * at least temporarily in romstage and ramstage as the Intel Graphics Device + * Base Address Range 0. */ +#define IGD_BASE_ADDRESS CONFIG_GFX_GMA_DEFAULT_MMIO +#define IGD_BASE_SIZE 0x1000000 + +/* * I/O port address space */ #define SMBUS_BASE_ADDRESS 0x0efa0 |