diff options
| -rw-r--r-- | src/soc/intel/common/basecode/debug/debug_feature.c | 11 | ||||
| -rw-r--r-- | src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_lite.c | 21 |
3 files changed, 30 insertions, 5 deletions
diff --git a/src/soc/intel/common/basecode/debug/debug_feature.c b/src/soc/intel/common/basecode/debug/debug_feature.c index 42cf992afa..1c55f0b887 100644 --- a/src/soc/intel/common/basecode/debug/debug_feature.c +++ b/src/soc/intel/common/basecode/debug/debug_feature.c @@ -10,7 +10,8 @@ #define SI_DESC_REGION_SZ 4096 struct pre_mem_ft { - uint8_t reserved[64]; + uint8_t cse_fw_update_disable; /* Byte location: 0xF00 */ + uint8_t reserved[63]; }; static struct pre_mem_ft pre_mem_debug; @@ -18,6 +19,14 @@ static struct pre_mem_ft pre_mem_debug; _Static_assert(sizeof(struct pre_mem_ft) % 64 == 0 && sizeof(struct pre_mem_ft) <= 256, "sizeof(struct pre_mem_ft) must be a multiple of 64 bytes and up to 256 bytes"); +bool is_debug_cse_fw_update_disable(void) +{ + printk(BIOS_DEBUG, "rt_debug: pre_mem_debug.cse_fw_update_disable=%d\n", + pre_mem_debug.cse_fw_update_disable); + + return pre_mem_debug.cse_fw_update_disable == 1; +} + uint8_t pre_mem_debug_init(void) { if (spi_flash_read(boot_device_spi_flash(), PRE_MEM_FEATURE_CTRL_OFFSET, diff --git a/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h index fabf27ddd8..51e3f4d05a 100644 --- a/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h +++ b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h @@ -5,6 +5,9 @@ #include <types.h> +/* Check if CSE firmware update is enabled or not */ +bool is_debug_cse_fw_update_disable(void); + /* * Reads OEM Section area in the Descriptor Region and * populates pre_mem_debug structure. diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index ca6d7d3e82..83f5eb1e84 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1,15 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/cpu.h> #include <console/console.h> #include <cbfs.h> #include <commonlib/region.h> #include <fmap.h> #include <intelblocks/cse.h> #include <intelblocks/cse_layout.h> +#include <intelbasecode/debug_feature.h> #include <security/vboot/vboot_common.h> #include <security/vboot/misc.h> #include <soc/intel/common/reset.h> -#include <arch/cpu.h> #define BPDT_HEADER_SZ sizeof(struct bpdt_header) #define BPDT_ENTRY_SZ sizeof(struct bpdt_entry) @@ -663,6 +664,17 @@ static bool cse_write_rw_region(const struct region_device *target_rdev, return true; } +static bool is_cse_fw_update_enabled(void) +{ + if (!CONFIG(SOC_INTEL_CSE_RW_UPDATE)) + return false; + + if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) + return !is_debug_cse_fw_update_disable(); + + return true; +} + static enum csme_failure_reason cse_update_rw(const struct cse_bp_info *cse_bp_info, const void *cse_cbfs_rw, const size_t cse_blob_sz, struct region_device *target_rdev) @@ -1079,10 +1091,11 @@ void cse_fw_sync(void) cse_trigger_vboot_recovery(CSE_LITE_SKU_DATA_WIPE_ERROR); /* - * If SOC_INTEL_CSE_RW_UPDATE is defined , then trigger CSE firmware update. The driver - * triggers recovery if CSE CBFS RW metadata or CSE CBFS RW blob is not available. + * cse firmware update is skipped if SOC_INTEL_CSE_RW_UPDATE is not defined and + * runtime debug control flag is not enabled. The driver triggers recovery if CSE CBFS + * RW metadata or CSE CBFS RW blob is not available. */ - if (CONFIG(SOC_INTEL_CSE_RW_UPDATE)) { + if (is_cse_fw_update_enabled()) { uint8_t rv; rv = cse_fw_update(&cse_bp_info.bp_info); if (rv) |