diff options
8 files changed, 141 insertions, 78 deletions
diff --git a/src/mainboard/google/hatch/bootblock.c b/src/mainboard/google/hatch/bootblock.c index 9534af11d9..15dfe933eb 100644 --- a/src/mainboard/google/hatch/bootblock.c +++ b/src/mainboard/google/hatch/bootblock.c @@ -19,18 +19,11 @@ static void early_config_gpio(void) { - const struct pad_config *base_early_table; - const struct pad_config *override_early_table; - size_t base_gpios; - size_t override_gpios; + const struct pad_config *variant_early_table; + size_t variant_gpios; - base_early_table = base_early_gpio_table(&base_gpios); - override_early_table = override_early_gpio_table(&override_gpios); - - gpio_configure_pads_with_override(base_early_table, - base_gpios, - override_early_table, - override_gpios); + variant_early_table = variant_early_gpio_table(&variant_gpios); + gpio_configure_pads(variant_early_table, variant_gpios); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 38d44f336b..fcb1a614cc 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -426,48 +426,6 @@ const struct pad_config *__weak variant_sleep_gpio_table( return default_sleep_gpio_table; } -/* GPIOs needed prior to ramstage. */ -static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), - /* F2 : MEM_CH_SEL */ - PAD_CFG_GPI(GPP_F2, NONE, PLTRST), - /* F11 : PCH_MEM_STRAP2 */ - PAD_CFG_GPI(GPP_F11, NONE, PLTRST), - /* F20 : PCH_MEM_STRAP0 */ - PAD_CFG_GPI(GPP_F20, NONE, PLTRST), - /* F21 : PCH_MEM_STRAP1 */ - PAD_CFG_GPI(GPP_F21, NONE, PLTRST), - /* F22 : PCH_MEM_STRAP3 */ - PAD_CFG_GPI(GPP_F22, NONE, PLTRST), -}; - -const struct pad_config *base_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), @@ -485,9 +443,3 @@ const struct pad_config *__weak override_gpio_table(size_t *num) *num = 0; return NULL; } - -const struct pad_config *__weak override_early_gpio_table(size_t *num) -{ - *num = 0; - return NULL; -} diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 71a2362b00..920e428484 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -23,13 +23,11 @@ /* * The next set of functions return the gpio table and fill in the number of - * entries for each table. The "base" GPIOs live in the "hatch" variant, and + * entries for each table. The "base" GPIOs live in the "baseboard" variant, and * the overrides live with the specific board (kohaku, kled, etc.). */ const struct pad_config *base_gpio_table(size_t *num); -const struct pad_config *base_early_gpio_table(size_t *num); const struct pad_config *override_gpio_table(size_t *num); -const struct pad_config *override_early_gpio_table(size_t *num); /* Return board specific memory configuration */ void variant_memory_params(struct cnl_mb_cfg *bcfg); @@ -40,6 +38,9 @@ int variant_memory_sku(void); /* Return variant specific gpio pads to be configured during sleep */ const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num); +/* Return GPIO pads that need to be configured before ramstage */ +const struct pad_config *variant_early_gpio_table(size_t *num); + /* Return ChromeOS gpio table and fill in number of entries. */ const struct cros_gpio *variant_cros_gpios(size_t *num); diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc index 555cbb463c..a990b5ad05 100644 --- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc @@ -20,3 +20,4 @@ SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index f95e0220f1..56f587b6b8 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -27,3 +27,43 @@ const struct pad_config *override_gpio_table(size_t *num) *num = ARRAY_SIZE(gpio_table); return gpio_table; } + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 257b020065..0ad3967ee9 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -107,12 +107,39 @@ const struct pad_config *override_gpio_table(size_t *num) return gpio_table; } -/* GPIOs configured before ramstage */ +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ static const struct pad_config early_gpio_table[] = { - PAD_NC(GPP_C23, NONE), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), }; -const struct pad_config *override_early_gpio_table(size_t *num) +const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index f6aeb690c5..d6525e6564 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -59,19 +59,41 @@ const struct pad_config *override_gpio_table(size_t *num) return gpio_table; } -/* GPIOs configured before ramstage */ +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ static const struct pad_config early_gpio_table[] = { - /* F3 : MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_F3, NONE, PLTRST), - /* F10 : MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_F10, NONE, PLTRST), - /* H19 : MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_H19, NONE, PLTRST), - /* H22 : MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_H22, NONE, PLTRST), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), }; -const struct pad_config *override_early_gpio_table(size_t *num) +const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index c157178966..53a58c9df7 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -81,12 +81,39 @@ const struct pad_config *override_gpio_table(size_t *num) return gpio_table; } -/* GPIOs configured before ramstage */ +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ static const struct pad_config early_gpio_table[] = { - PAD_NC(GPP_C23, NONE), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), }; -const struct pad_config *override_early_gpio_table(size_t *num) +const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; |