diff options
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/cml/devicetree.cb | 98 |
1 files changed, 49 insertions, 49 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index 9a71015ae7..5757439d9a 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -53,15 +53,15 @@ chip soc/intel/cannonlake device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on # SA Thermal Device + device ref system_agent on end + device ref igpu on end + device ref dptf on register "Device4Enable" = "1" end - device pci 12.0 off end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on # USB xHCI + device ref thermal off end + device ref ufs off end + device ref gspi2 off end + device ref xhci on # Motherboard USB Type C register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" @@ -83,16 +83,16 @@ chip soc/intel/cannonlake # Internal Bluetooth register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" end - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # SRAM - device pci 14.3 on # CNVi + device ref xdci off end + device ref shared_sram on end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device generic 0 on end end end - device pci 14.5 off end # SDCard - device pci 15.0 on # I2C0 + device ref sdxc off end + device ref i2c0 on chip drivers/i2c/hid register "generic.hid" = ""STAR0001"" register "generic.desc" = ""Touchpad"" @@ -102,34 +102,34 @@ chip soc/intel/cannonlake device i2c 2c on end end end - device pci 15.1 off end # I2C1 - device pci 15.2 off end # I2C2 - device pci 15.3 off end # I2C3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on # SATA + device ref i2c1 off end + device ref i2c2 off end + device ref i2c3 off end + device ref heci1 on end + device ref heci2 off end + device ref csme_ider off end + device ref csme_ktr off end + device ref heci3 off end + device ref heci4 off end + device ref sata on register "SataSalpSupport" = "1" # Port 1 register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" end - device pci 19.0 on end # I2C4 - device pci 19.1 off end # I2C5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 (SSD x4) + device ref i2c4 on end + device ref i2c5 off end + device ref uart2 on end + device ref emmc off end + device ref pcie_rp1 off end + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 off end + device ref pcie_rp9 on # SSD x4 register "PcieRpSlotImplemented[8]" = "1" register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" @@ -137,14 +137,14 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[1]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on # LPC Interface + device ref pcie_rp10 off end + device ref pcie_rp11 off end + device ref pcie_rp12 off end + device ref uart0 off end + device ref uart1 off end + device ref gspi0 off end + device ref gspi1 off end + device ref lpc_espi on register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" register "gen3_dec" = "0x00fc0201" @@ -174,14 +174,14 @@ chip soc/intel/cannonlake device pnp 4e.19 off end # Power Management Channel 5 end end - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on # Intel HDA + device ref p2sb on end + device ref pmc hidden end + device ref hda on register "PchHdaAudioLinkHda" = "1" end - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device ref smbus on end + device ref fast_spi on end + device ref gbe off end end chip drivers/crb device mmio 0xfed40000 on end |