diff options
| -rw-r--r-- | src/mainboard/pcengines/apu1/Kconfig | 30 | ||||
| -rw-r--r-- | src/mainboard/pcengines/apu1/devicetree.cb | 5 | ||||
| -rw-r--r-- | src/mainboard/pcengines/apu1/mainboard.c | 27 |
3 files changed, 61 insertions, 1 deletions
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 9409bc3cd1..197dbc0f6b 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -82,4 +82,34 @@ config DRIVERS_PS2_KEYBOARD bool default n +choice + prompt "J19 pins 1-10" + default PINMUX_OFF_C + +config PINMUX_OFF_C + bool "disable" + +config PINMUX_GPIO0 + bool "GPIO" + +config PINMUX_UART_C + bool "UART 0x3e8" + +endchoice + +choice + prompt "J19 pins 11-20" + default PINMUX_OFF_D + +config PINMUX_OFF_D + bool "disable" + +config PINMUX_GPIO1 + bool "GPIO" + +config PINMUX_UART_D + bool "UART 0x2e8" + +endchoice + endif # BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index b98f34d4d1..1f07a9b016 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -59,16 +59,19 @@ chip northbridge/amd/agesa/family14/root_complex irq 0x70 = 3 end device pnp 2e.10 off + # UART C is conditionally turned on io 0x60 = 0x3e8 irq 0x70 = 4 end device pnp 2e.11 off + # UART D is conditionally turned on io 0x60 = 0x2e8 irq 0x70 = 3 end device pnp 2e.8 off end device pnp 2e.f off end - device pnp 2e.7 off end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 off end device pnp 2e.107 off end device pnp 2e.607 off end device pnp 2e.e off end diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 3b8541cae1..f49059d871 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -33,6 +33,7 @@ #include "SBPLATFORM.h" #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> #include "gpio_ftns.h" void set_pcie_reset(void); @@ -135,6 +136,30 @@ static void pirq_setup(void) picr_data_ptr = mainboard_picr_data; } +/* Wrapper to enable GPIO/UART devices under menuconfig. Revisit + * once configuration file format for SPI flash storage is complete. + */ +#define SIO_PORT 0x2e + +static void config_gpio_mux(void) +{ + struct device *uart, *gpio; + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); + gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0); + if (uart) + uart->enabled = CONFIG_PINMUX_UART_C; + if (gpio) + gpio->enabled = CONFIG_PINMUX_GPIO0; + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); + gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1); + if (uart) + uart->enabled = CONFIG_PINMUX_UART_D; + if (gpio) + gpio->enabled = CONFIG_PINMUX_GPIO1; +} + /** * TODO * SB CIMx callback @@ -158,6 +183,8 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + config_gpio_mux(); + /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } |