diff options
| -rw-r--r-- | src/northbridge/intel/gm45/gma.c | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/gma.c | 6 |
2 files changed, 0 insertions, 18 deletions
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 30c8d9a6e1..8596193057 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -305,14 +305,8 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, write32(mmio + PIPE_LINK_M1(0), link_m1); write32(mmio + PIPE_LINK_N1(0), link_n1); - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); - write32(mmio + 0x000f0008, 0x00000040); - write32(mmio + 0x000f000c, 0x00022050); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); @@ -598,14 +592,8 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, write32(mmio + PIPE_LINK_M1(0), link_m1); write32(mmio + PIPE_LINK_N1(0), link_n1); - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); - write32(mmio + 0x000f0008, 0x00000040); - write32(mmio + 0x000f000c, 0x00022050); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 3f3ba2bf26..749a7c827a 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -311,14 +311,8 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, write32(mmio + PIPE_LINK_M1(0), link_m1); write32(mmio + PIPE_LINK_N1(0), link_n1); - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); - write32(mmio + 0x000f0008, 0x00000040); - write32(mmio + 0x000f000c, 0x00022050); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); |