diff options
| -rw-r--r-- | src/soc/intel/braswell/cpu.c | 10 | ||||
| -rw-r--r-- | src/soc/intel/braswell/include/soc/iosf.h | 6 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index e648ce04a3..2ab8725818 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -30,6 +30,7 @@ #include <cpu/x86/smm.h> #include <soc/intel/common/memmap.h> #include <reg_script.h> +#include <soc/iosf.h> #include <soc/msr.h> #include <soc/pattrs.h> #include <soc/ramstage.h> @@ -86,6 +87,7 @@ void soc_init_cpus(device_t dev) const struct pattrs *pattrs = pattrs_get(); struct mp_params mp_params; void *default_smm_area; + uint32_t bsmrwac; printk(BIOS_SPEW, "%s/%s ( %s )\n", __FILE__, __func__, dev_name(dev)); @@ -104,6 +106,14 @@ void soc_init_cpus(device_t dev) default_smm_area = backup_default_smm_area(); + /* + * Configure the BUNIT to allow dirty cache line evictions in non-SMM + * mode for the lines that were dirtied while in SMM mode. Otherwise + * the writes would be silently dropped. + */ + bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; + iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); + /* Set package MSRs */ reg_script_run(package_msr_script); diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index 1cdfb8f587..cf56a05491 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -131,9 +131,15 @@ void reg_script_write_iosf(struct reg_script_context *ctx); #define BUNIT_MMCONF_REG 0x27 #define BUNIT_BMISC 0x28 /* The SMMRR registers define the SMM region in MiB granularity. */ +#define BUNIT_SMRWAC 0x2d #define BUNIT_SMRRL 0x2e #define BUNIT_SMRRH 0x2f +/* SA ID bits. */ +#define SAI_IA_UNTRUSTED (1 << 0) +#define SAI_IA_SMM (1 << 2) +#define SAI_IA_BOOT (1 << 4) + /* * LPSS Registers */ |