diff options
48 files changed, 234 insertions, 192 deletions
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index d38c552b91..572ef999a5 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -17,6 +17,10 @@ #include "option_table.h" #endif +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) +#include <northbridge/amd/amdk8/f.h> +#endif + typedef void (*process_ap_t) (u32 apicid, void *gp); //core_range = 0 : all cores diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 89456404bd..0e21475c8f 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -33,22 +33,20 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" -#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ #include <northbridge/amd/amdk8/f.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 55771f9b1e..b22dec19ee 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -33,17 +33,16 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ #include <northbridge/amd/amdk8/f.h> unsigned get_sbdn(unsigned bus); #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } @@ -51,7 +50,6 @@ static inline int spd_read_byte(u32 device, u32 address) #include "southbridge/amd/rs780/early_setup.c" #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index a8242ec837..8578cd1a3a 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -31,20 +31,18 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" -#include "northbridge/amd/amdk8/debug.c" /* After sb600/early_setup.c! */ #include <northbridge/amd/amdk8/f.h> -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 5e0123b5b4..9fac7cf0f9 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -26,7 +26,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> #include <delay.h> -#include "northbridge/amd/amdk8/debug.c" + #include <cpu/amd/mtrr.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> @@ -44,9 +44,9 @@ static void memreset_setup(void) outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 int ret,i; @@ -60,7 +60,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_write_byte(SMBUS_HUB, 0x03, 0); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } @@ -69,7 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 0894af9e53..1894fdefb9 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -34,7 +34,6 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ #include <northbridge/amd/amdk8/pre_f.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) @@ -42,10 +41,10 @@ unsigned get_sbdn(unsigned bus); -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index d10fe9aaac..f58729d433 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -38,7 +38,7 @@ #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> -#include "northbridge/amd/amdk8/debug.c" + #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -46,10 +46,10 @@ #include <spd.h> #include <northbridge/amd/amdk8/pre_f.h> -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index c6ea08da26..04edc7e8b2 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -38,7 +38,6 @@ unsigned int get_sbdn(unsigned bus); #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <southbridge/via/vt8237r/vt8237r.h> -#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -48,10 +47,10 @@ unsigned int get_sbdn(unsigned bus); #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index f2465d03c8..fb3bb57229 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -38,7 +38,6 @@ unsigned int get_sbdn(unsigned bus); #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <southbridge/via/vt8237r/vt8237r.h> -#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -48,10 +47,10 @@ unsigned int get_sbdn(unsigned bus); #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index a0565a9ce7..83194fc3e9 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -38,7 +38,6 @@ unsigned int get_sbdn(unsigned bus); #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83697hf/w83697hf.h> #include <southbridge/via/vt8237r/vt8237r.h> -#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -46,10 +45,10 @@ unsigned int get_sbdn(unsigned bus); #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index d7bebbb702..c38164e12b 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -35,7 +35,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> #include <delay.h> -#include "northbridge/amd/amdk8/debug.c" + #include <cpu/amd/mtrr.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> @@ -44,11 +44,9 @@ unsigned int get_sbdn(unsigned bus); #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } - -static void activate_spd_rom(const struct mem_controller *ctrl); +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -56,7 +54,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -181,7 +178,8 @@ static const uint16_t spd_addr[] = { RC01 | DIMM0, RC01 | DIMM2, RC01 | DIMM4, RC01 | DIMM6, RC01 | DIMM1, RC01 | DIMM3, RC01 | DIMM5, RC01 | DIMM7, }; -static void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) +{ printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 91fded1e05..7bf8306813 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -36,7 +36,7 @@ #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) @@ -55,10 +55,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) {} -static inline void activate_spd_rom(const struct mem_controller *ctrl) {} +void memreset(int controllers, const struct mem_controller *ctrl) {} +void activate_spd_rom(const struct mem_controller *ctrl) {} -static inline int spd_read_byte(unsigned int device, unsigned int address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } @@ -67,7 +67,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 8aea021081..25eedbabeb 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -34,7 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <southbridge/via/vt8237r/vt8237r.h> @@ -46,10 +46,10 @@ unsigned int get_sbdn(unsigned bus); #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -58,7 +58,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index e8053424e3..3b6990b2c5 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -34,7 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <southbridge/via/vt8237r/vt8237r.h> @@ -48,10 +48,10 @@ unsigned int get_sbdn(unsigned bus); #define IT8712F_GPIO_BASE 0x0a20 -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -60,7 +60,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index a67ae46066..b618b52049 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -13,7 +13,7 @@ #include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -24,16 +24,16 @@ unsigned get_sbdn(unsigned bus); static void memreset_setup(void) { } -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x71 unsigned device=(ctrl->channel0[0])>>8; smbus_send_byte(SMBUS_HUB, device); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 337423fbd8..0414df1142 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -37,17 +37,17 @@ #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/sis/sis966/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -55,7 +55,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index da96ed70c5..c58b526e9b 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -34,7 +34,6 @@ #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) @@ -53,10 +52,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -75,7 +74,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 46831322e8..5420df13ef 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -16,7 +16,7 @@ #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> @@ -39,7 +39,7 @@ static void memreset_setup(void) } } -static void memreset(int controllers, const struct mem_controller *ctrl) +void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); @@ -51,7 +51,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { int ret,i; unsigned device=(ctrl->channel0[0])>>8; @@ -76,7 +76,7 @@ static inline void change_i2c_mux(unsigned device) printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index e7a3b2f36e..6ccaf95d92 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -39,7 +39,7 @@ #include <superio/serverengines/pilot/pilot.h> #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) @@ -47,9 +47,9 @@ unsigned get_sbdn(unsigned bus); -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 @@ -58,7 +58,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -67,7 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include <spd.h> #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index a31ecefbaa..9723ad2277 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> #include <delay.h> -#include "northbridge/amd/amdk8/debug.c" + #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -39,7 +39,7 @@ static void memreset_setup(void) } } -static void memreset(int controllers, const struct mem_controller *ctrl) +void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); @@ -49,9 +49,9 @@ static void memreset(int controllers, const struct mem_controller *ctrl) } } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 8a01e6b317..55ac1bcabb 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -28,7 +28,7 @@ #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <cpu/amd/mtrr.h> @@ -38,17 +38,16 @@ #include "southbridge/amd/sb600/early_setup.c" #include <northbridge/amd/amdk8/f.h> -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 25c4a403ef..1da2ff4d3c 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -35,7 +35,7 @@ #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> -#include "northbridge/amd/amdk8/debug.c" + #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -49,10 +49,10 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index d1c50df33f..35c8943676 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -36,7 +36,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) @@ -54,10 +54,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) {} -static inline void activate_spd_rom(const struct mem_controller *ctrl) {} +void memreset(int controllers, const struct mem_controller *ctrl) {} +void activate_spd_rom(const struct mem_controller *ctrl) {} -static inline int spd_read_byte(unsigned int device, unsigned int address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } @@ -66,7 +66,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index db5242926a..141c7e0fd3 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -35,7 +35,7 @@ #include <reset.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -45,9 +45,9 @@ unsigned get_sbdn(unsigned bus); -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 @@ -56,7 +56,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -65,7 +65,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 463a7679d0..afb82eba72 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -32,7 +32,7 @@ #include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <cpu/x86/bist.h> @@ -55,9 +55,9 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 @@ -66,7 +66,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -75,7 +75,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index ac070e9925..9ae0ed4397 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -35,7 +35,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) @@ -53,10 +53,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -65,7 +65,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 15ba45f1b1..4411368704 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -40,31 +40,29 @@ #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" -#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ #include <northbridge/amd/amdk8/f.h> #define SERIAL_DEV PNP_DEV(0x2e, CONFIG_UART_FOR_CONSOLE == 1 ? IT8712F_SP2 : IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ -static void memreset(int controllers, const struct mem_controller *ctrl) +void memreset(int controllers, const struct mem_controller *ctrl) { } /* called in raminit_f.c */ -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { } /*called in raminit_f.c */ -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index a1659b7f84..7df486a438 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -15,7 +15,7 @@ #include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/smsc/lpc47b397/lpc47b397.h> #include <cpu/x86/bist.h> #include "superio/smsc/lpc47b397/early_gpio.c" @@ -26,7 +26,7 @@ #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) #define SUPERIO_GPIO_IO_BASE 0x400 -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } #ifdef ENABLE_ONBOARD_SCSI static void sio_gpio_setup(void) @@ -40,9 +40,9 @@ static void sio_gpio_setup(void) } #endif -static inline void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 6c3fdbd4e6..576ca6b562 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -34,7 +34,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include <superio/smsc/dme1737/dme1737.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1) @@ -52,10 +52,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -64,7 +64,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index fdfb124fcb..60c38454a2 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -32,7 +32,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -51,9 +51,9 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #if 0 /* We don't do any switching yet. */ @@ -65,7 +65,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) #endif } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -74,7 +74,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 89cea08a9a..bc0a3ec0da 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -35,7 +35,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -54,10 +54,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -66,7 +66,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index e534617e4d..4ffafb11df 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -27,7 +27,7 @@ #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/x86/bist.h> @@ -38,17 +38,16 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index d5a4784ced..7f41536277 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -27,7 +27,7 @@ #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/x86/bist.h> @@ -39,17 +39,16 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 02b4680287..97655aab80 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -35,7 +35,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -53,10 +53,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -65,7 +65,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 2fe96a7f8c..327e592c83 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -15,7 +15,6 @@ #include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/x86/bist.h> @@ -25,10 +24,10 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) static void memreset_setup(void) { } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc index 7497a07437..fb2aca5cc3 100644 --- a/src/northbridge/amd/amdk8/Makefile.inc +++ b/src/northbridge/amd/amdk8/Makefile.inc @@ -4,8 +4,11 @@ ramstage-y += northbridge.c ramstage-y += misc_control.c ramstage-y += get_sblk_pci1234.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c + +romstage-y += debug.c ifeq ($(CONFIG_K8_REV_F_SUPPORT),y) romstage-$(CONFIG_HAVE_ACPI_RESUME) += exit_from_self.c +romstage-y += raminit_f.c endif # Enable this if you want to check the values of the PCI routing registers. diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index a8431f4df2..e1eade4265 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -3,7 +3,13 @@ * */ -static inline void print_debug_addr(const char *str, void *val) +#include "debug.h" +#include <console/console.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <delay.h> + +void print_debug_addr(const char *str, void *val) { #if CONFIG_DEBUG_CAR printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val); @@ -11,12 +17,12 @@ static inline void print_debug_addr(const char *str, void *val) } #if 1 -static void print_debug_pci_dev(unsigned dev) +void print_debug_pci_dev(unsigned dev) { printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); } -static inline void print_pci_devices(void) +void print_pci_devices(void) { pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); @@ -41,7 +47,7 @@ static inline void print_pci_devices(void) } } -static void dump_pci_device(unsigned dev) +void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); @@ -58,9 +64,7 @@ static void dump_pci_device(unsigned dev) } #if CONFIG_K8_REV_F_SUPPORT -static uint32_t pci_read_config32_index_wait(pci_devfn_t dev, - uint32_t index_reg, uint32_t index); -static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) +void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { int i; print_debug_pci_dev(dev); @@ -81,7 +85,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) } #endif -static inline void dump_pci_devices(void) +void dump_pci_devices(void) { pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); @@ -106,7 +110,7 @@ static inline void dump_pci_devices(void) } } -static inline void dump_pci_devices_on_bus(unsigned busn) +void dump_pci_devices_on_bus(unsigned busn) { pci_devfn_t dev; for (dev = PCI_DEV(busn, 0, 0); @@ -133,7 +137,7 @@ static inline void dump_pci_devices_on_bus(unsigned busn) #if CONFIG_DEBUG_SMBUS -static void dump_spd_registers(const struct mem_controller *ctrl) +void dump_spd_registers(const struct mem_controller *ctrl) { int i; printk(BIOS_DEBUG, "\n"); @@ -179,7 +183,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) } } } -static void dump_smbus_registers(void) +void dump_smbus_registers(void) { unsigned device; printk(BIOS_DEBUG, "\n"); @@ -205,7 +209,7 @@ static void dump_smbus_registers(void) } #endif -static inline void dump_io_resources(unsigned port) +void dump_io_resources(unsigned port) { int i; @@ -225,7 +229,7 @@ static inline void dump_io_resources(unsigned port) } } -static inline void dump_mem(unsigned start, unsigned end) +void dump_mem(unsigned start, unsigned end) { unsigned i; printk(BIOS_DEBUG, "dump_mem:"); diff --git a/src/northbridge/amd/amdk8/debug.h b/src/northbridge/amd/amdk8/debug.h new file mode 100644 index 0000000000..06ed51923b --- /dev/null +++ b/src/northbridge/amd/amdk8/debug.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef AMDK8_DEBUG_H +#define AMDK8_DEBUG_H + +#include <inttypes.h> +#include <arch/io.h> + +void print_debug_addr(const char *str, void *val); +void print_debug_pci_dev(unsigned int dev); +void print_pci_devices(void); +void dump_pci_device(unsigned int dev); +void dump_pci_device_index_wait(unsigned int dev, uint32_t index_reg); +uint32_t pci_read_config32_index_wait(pci_devfn_t dev, + uint32_t index_reg, uint32_t index); +void dump_pci_devices(void); +void dump_pci_devices_on_bus(unsigned int busn); +void dump_io_resources(unsigned int port); +void dump_mem(unsigned start, unsigned end); + +#endif diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index 506a44970c..f3f9c42614 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -585,5 +585,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) #endif void dqs_restore_MC_NVRAM(unsigned int dev); +void train_ram_on_node(unsigned nodeid, unsigned coreid, + struct sys_info *sysinfo, unsigned retcall); #endif /* AMDK8_F_H */ diff --git a/src/northbridge/amd/amdk8/f_pci.c b/src/northbridge/amd/amdk8/f_pci.c index 3ea4003294..230333ab4f 100644 --- a/src/northbridge/amd/amdk8/f_pci.c +++ b/src/northbridge/amd/amdk8/f_pci.c @@ -1,6 +1,8 @@ #ifndef AMDK8_F_PCI_C #define AMDK8_F_PCI_C +#include "debug.h" + #ifdef UNUSED_CODE /* bit [10,8] are dev func, bit[1,0] are dev index */ static uint32_t pci_read_config32_index(pci_devfn_t dev, uint32_t index_reg, @@ -24,7 +26,7 @@ static void pci_write_config32_index(pci_devfn_t dev, uint32_t index_reg, } #endif -static uint32_t pci_read_config32_index_wait(pci_devfn_t dev, +uint32_t pci_read_config32_index_wait(pci_devfn_t dev, uint32_t index_reg, uint32_t index) { uint32_t dword; diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index b10cd0ef43..168f7ce437 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -42,9 +42,9 @@ static int controller_present(const struct mem_controller *ctrl) } #if CONFIG_RAMINIT_SYSINFO -static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) +void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) #else -static void sdram_set_registers(const struct mem_controller *ctrl) +void sdram_set_registers(const struct mem_controller *ctrl) #endif { static const unsigned int register_values[] = { @@ -2167,9 +2167,9 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct } #if CONFIG_RAMINIT_SYSINFO -static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) +void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) #else -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +void sdram_set_spd_registers(const struct mem_controller *ctrl) #endif { struct spd_set_memclk_result result; @@ -2326,9 +2326,9 @@ void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) #endif #if CONFIG_RAMINIT_SYSINFO -static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) +void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) #else -static void sdram_enable(int controllers, const struct mem_controller *ctrl) +void sdram_enable(int controllers, const struct mem_controller *ctrl) #endif { int i; @@ -2466,7 +2466,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } -static void set_sysinfo_in_ram(unsigned val) +void set_sysinfo_in_ram(unsigned val) { } diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h index 95a99b0d7f..0f4636b43e 100644 --- a/src/northbridge/amd/amdk8/raminit.h +++ b/src/northbridge/amd/amdk8/raminit.h @@ -1,6 +1,9 @@ #ifndef RAMINIT_H #define RAMINIT_H +#define NODE_ID 0x60 +#define HT_INIT_CONTROL 0x6c + #define NODE_NUMS 8 #define DIMM_SOCKETS 4 @@ -12,15 +15,28 @@ struct mem_controller { }; struct sys_info; + void exit_from_self(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo); void setup_resource_map(const unsigned int *register_values, int max); void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +void activate_spd_rom(const struct mem_controller *ctrl); +void memreset(int controllers, const struct mem_controller *ctrl); +void set_sysinfo_in_ram(unsigned int val); #define TIMEOUT_LOOPS 300000 #if defined(__PRE_RAM__) && CONFIG_RAMINIT_SYSINFO void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo); +void sdram_enable(int controllers, const struct mem_controller *ctrl, + struct sys_info *sysinfo); +void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo); +void sdram_set_spd_registers(const struct mem_controller *ctrl, + struct sys_info *sysinfo); #else +void sdram_set_registers(const struct mem_controller *ctrl); +void sdram_set_spd_registers(const struct mem_controller *ctrl); +void sdram_enable(int controllers, const struct mem_controller *ctrl); void sdram_initialize(int controllers, const struct mem_controller *ctrl); #endif diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index d6632bbef5..a97989687a 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -16,14 +16,20 @@ * GNU General Public License for more details. */ +#include <arch/io.h> +#include <console/console.h> #include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/tsc.h> #include <cpu/amd/mtrr.h> +#include <pc80/mc146818rtc.h> #include <lib.h> #include <stdlib.h> +#include <string.h> #include <arch/acpi.h> +#include "amdk8.h" #include "raminit.h" #include "f.h" #include <spd_ddr2.h> @@ -90,7 +96,7 @@ static int controller_present(const struct mem_controller *ctrl) return pci_read_config32(ctrl->f0, 0) == 0x11001022; } -static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) +void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) { static const unsigned int register_values[] = { @@ -2791,7 +2797,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, return meminfo->dimm_mask; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl, +void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) { struct spd_set_memclk_result result; @@ -2971,7 +2977,7 @@ void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) } #endif -static void sdram_enable(int controllers, const struct mem_controller *ctrl, +void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) { int i; diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 1e99f338c7..c470b25425 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -17,6 +17,12 @@ #include <arch/stages.h> #include <cpu/x86/cr.h> #include <cpu/x86/mtrr.h> +#include <arch/early_variables.h> +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) +#include <southbridge/amd/sb700/sb700.h> +#else /* IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_K8T890) */ +#include <southbridge/via/k8t890/k8t890.h> +#endif //0: mean no debug info #define DQS_TRAIN_DEBUG 0 @@ -1769,7 +1775,7 @@ static void wait_till_sysinfo_in_ram(void) } #endif -static void set_sysinfo_in_ram(unsigned val) +void set_sysinfo_in_ram(unsigned val) { #if CONFIG_MEM_TRAIN_SEQ == 1 set_htic_bit(0, val, 9); @@ -2034,7 +2040,7 @@ static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info } -static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) +void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if (coreid) return; // only do it on core0 struct sys_info *sysinfox; diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c index 3d0b0f46bd..a17f197ccc 100644 --- a/src/northbridge/amd/amdk8/raminit_test.c +++ b/src/northbridge/amd/amdk8/raminit_test.c @@ -167,7 +167,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl) /* Nothing to do */ } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ } diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index d8734a9a72..f998c48b56 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -1,7 +1,6 @@ #include <stdint.h> #include <cpu/x86/lapic.h> -#define NODE_ID 0x60 -#define HT_INIT_CONTROL 0x6c +#include "raminit.h" #define HTIC_ColdR_Detect (1<<4) #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index 22a6a47ab4..dca75f40b2 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -134,7 +134,7 @@ u8 k8t890_early_setup_ht(void) return 1; } -static inline int s3_save_nvram_early(u32 dword, int size, int nvram_pos) +int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); @@ -155,7 +155,7 @@ static inline int s3_save_nvram_early(u32 dword, int size, int nvram_pos) return nvram_pos; } -static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) +int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { switch (size) { case 1: diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h index 548dd9e80a..8bc76ba927 100644 --- a/src/southbridge/via/k8t890/k8t890.h +++ b/src/southbridge/via/k8t890/k8t890.h @@ -37,6 +37,8 @@ #ifdef __PRE_RAM__ u8 k8t890_early_setup_ht(void); +int s3_save_nvram_early(u32 dword, int size, int nvram_pos); +int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); #define k8x8xx_early_setup_ht() k8t890_early_setup_ht() #else #include <device/device.h> |