diff options
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 640026a739..9dcb26a759 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -16,12 +16,14 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <arch/cpu.h> #include <arch/io.h> #include <arch/symbols.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <device/pci_def.h> #include <fsp/api.h> #include <fsp/util.h> @@ -81,6 +83,7 @@ asmlinkage void car_stage_entry(void) struct range_entry fsp_mem, reg_car; struct postcar_frame pcf; size_t mrc_data_size; + uintptr_t top_of_ram; printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -122,6 +125,16 @@ asmlinkage void car_stage_entry(void) if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + /* cbmem_top() needs to be at least 16 MiB aligned */ + assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); + postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); + run_postcar_phase(&pcf); } |