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-rw-r--r--src/soc/intel/tigerlake/chip.h3
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h9
2 files changed, 10 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index d3062cc720..edc716064f 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -105,6 +105,9 @@ struct soc_intel_tigerlake_config {
/* Common struct containing power limits configuration information */
struct soc_power_limits_config power_limits_config[POWER_LIMITS_MAX];
+ /* Configuration for boot TDP selection; */
+ uint8_t ConfigTdpLevel;
+
/* Gpio group routed to each dword of the GPE0 block. Values are
* of the form PMC_GPP_[A:U] or GPD. */
uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
index 35cc43bcbb..909ba36708 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
@@ -1304,9 +1304,14 @@ typedef struct {
**/
UINT8 IsTPMPresence;
-/** Offset 0x0389 - Reserved
+/** Offset 0x0389 - ConfigTdpLevel
+ Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP Up;0xFF : Deactivate
**/
- UINT8 Reserved17[6];
+ UINT8 ConfigTdpLevel;
+
+/** Offset 0x038A - Reserved
+**/
+ UINT8 Reserved17[5];
/** Offset 0x038F - Enable PCH HSIO PCIE Rx Set Ctle
Enable PCH PCIe Gen 3 Set CTLE Value.