diff options
| -rw-r--r-- | src/arch/x86/postcar_loader.c | 4 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/ramstage.c | 23 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/silicon_init.c | 2 | ||||
| -rw-r--r-- | src/include/stage_cache.h | 10 | ||||
| -rw-r--r-- | src/lib/prog_loaders.c | 6 | ||||
| -rw-r--r-- | src/soc/amd/common/block/pi/refcode_loader.c | 9 |
6 files changed, 19 insertions, 35 deletions
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 241ba8c21f..cae5574fd3 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -9,7 +9,6 @@ #include <program_loading.h> #include <reset.h> #include <rmodule.h> -#include <romstage_handoff.h> #include <stage_cache.h> #include <timestamp.h> #include <security/vboot/vboot_common.h> @@ -183,8 +182,7 @@ void run_postcar_phase(struct postcar_frame *pcf) postcar_commit_mtrrs(pcf); - if (!CONFIG(NO_STAGE_CACHE) && - romstage_handoff_is_resume()) { + if (resume_from_stage_cache()) { stage_cache_load_stage(STAGE_POSTCAR, &prog); /* This is here to allow platforms to pass different stack parameters between S3 resume and normal boot. On the diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 45faa5507e..ddfc3c7e54 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -143,21 +143,6 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) soc_after_silicon_init(); } -static void fsp_cache_save(struct prog *fsp) -{ - if (CONFIG(NO_STAGE_CACHE)) - return; - - printk(BIOS_DEBUG, "FSP: Saving binary in cache\n"); - - if (prog_entry(fsp) == NULL) { - printk(BIOS_ERR, "ERROR: No FSP to save in cache.\n"); - return; - } - - stage_cache_add(STAGE_REFCODE, fsp); -} - static int fsp_find_and_relocate(struct prog *fsp) { if (prog_locate(fsp)) { @@ -176,14 +161,14 @@ static int fsp_find_and_relocate(struct prog *fsp) static void fsp_load(void) { struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); - int is_s3_wakeup = acpi_is_wakeup_s3(); - if (is_s3_wakeup && !CONFIG(NO_STAGE_CACHE)) { - printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); + if (resume_from_stage_cache()) { stage_cache_load_stage(STAGE_REFCODE, &fsp); } else { fsp_find_and_relocate(&fsp); - fsp_cache_save(&fsp); + + if (prog_entry(&fsp)) + stage_cache_add(STAGE_REFCODE, &fsp); } /* FSP_INFO_HEADER is set as the program entry. */ diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index a4ffbda4cc..08494603f5 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -205,7 +205,7 @@ void fsps_load(bool s3wake) if (load_done) return; - if (s3wake && !CONFIG(NO_STAGE_CACHE)) { + if (resume_from_stage_cache()) { printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n"); stage_cache_load_stage(STAGE_REFCODE, fsps); if (fsp_validate_component(&fsps_hdr, prog_rdev(fsps)) != CB_SUCCESS) diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index ba8827dad6..1e46b5cfe2 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -3,6 +3,7 @@ #ifndef _STAGE_CACHE_H_ #define _STAGE_CACHE_H_ +#include <romstage_handoff.h> #include <stddef.h> #include <stdint.h> #include <program_loading.h> @@ -38,6 +39,15 @@ static inline void stage_cache_get_raw(int stage_id, void **base, size_t *size) #endif +static inline int resume_from_stage_cache(void) +{ + if (CONFIG(NO_STAGE_CACHE)) + return 0; + + /* TBD: Replace this with acpi_is_wakeup_s3(). */ + return romstage_handoff_is_resume(); +} + /* Fill in parameters for the external stage cache, if utilized. */ void stage_cache_external_region(void **base, size_t *size); diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 93efc0a280..4722e54501 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -10,7 +10,6 @@ #include <lib.h> #include <program_loading.h> #include <reset.h> -#include <romstage_handoff.h> #include <rmodule.h> #include <stage_cache.h> #include <symbols.h> @@ -76,9 +75,6 @@ int __weak prog_locate_hook(struct prog *prog) { return 0; } static void run_ramstage_from_resume(struct prog *ramstage) { - if (!romstage_handoff_is_resume()) - return; - /* Load the cached ramstage to runtime location. */ stage_cache_load_stage(STAGE_RAMSTAGE, ramstage); @@ -119,7 +115,7 @@ void run_ramstage(void) * Only x86 systems using ramstage stage cache currently take the same * firmware path on resume. */ - if (ENV_X86 && !CONFIG(NO_STAGE_CACHE)) + if (ENV_X86 && resume_from_stage_cache()) run_ramstage_from_resume(&ramstage); vboot_run_logic(); diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c index 2fdbe83347..274291de56 100644 --- a/src/soc/amd/common/block/pi/refcode_loader.c +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -48,9 +48,7 @@ static int agesa_locate_stage_file_ramstage(const char *name, .prog = &prog, }; - if (acpi_is_wakeup_s3() && !CONFIG(NO_STAGE_CACHE)) { - printk(BIOS_INFO, "AGESA: Loading stage from cache\n"); - // There is no way to tell if this succeeded. + if (resume_from_stage_cache()) { stage_cache_load_stage(STAGE_REFCODE, &prog); } else { if (prog_locate(&prog)) @@ -59,10 +57,7 @@ static int agesa_locate_stage_file_ramstage(const char *name, if (rmodule_stage_load(&rmod_agesa) < 0) return -1; - if (!CONFIG(NO_STAGE_CACHE)) { - printk(BIOS_INFO, "AGESA: Saving stage to cache\n"); - stage_cache_add(STAGE_REFCODE, &prog); - } + stage_cache_add(STAGE_REFCODE, &prog); } return rdev_chain(rdev, prog_rdev(&prog), 0, |