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-rw-r--r--src/cpu/intel/haswell/romstage.c3
-rw-r--r--src/drivers/intel/fsp1_1/romstage.c10
-rw-r--r--src/drivers/tpm/Kconfig7
-rw-r--r--src/drivers/tpm/Makefile.inc1
-rw-r--r--src/drivers/tpm/tpm.c35
-rw-r--r--src/mainboard/asus/kgpe-d16/romstage.c4
-rw-r--r--src/mainboard/google/link/romstage.c1
-rw-r--r--src/mainboard/google/parrot/romstage.c1
-rw-r--r--src/mainboard/google/rotor/Kconfig2
-rw-r--r--src/mainboard/google/stout/romstage.c1
-rw-r--r--src/mainboard/google/urara/Kconfig2
-rw-r--r--src/mainboard/intel/emeraldlake2/romstage.c1
-rw-r--r--src/mainboard/lenovo/x201/romstage.c4
-rw-r--r--src/mainboard/pcengines/apu2/romstage.c4
-rw-r--r--src/mainboard/samsung/lumpy/romstage.c1
-rw-r--r--src/mainboard/samsung/stumpy/romstage.c1
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c4
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c4
-rw-r--r--src/soc/intel/braswell/romstage/romstage.c1
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c4
20 files changed, 43 insertions, 48 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 0e91daee50..b30d4af8b0 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -42,7 +42,6 @@
#include "northbridge/intel/haswell/raminit.h"
#include "southbridge/intel/lynxpoint/pch.h"
#include "southbridge/intel/lynxpoint/me.h"
-#include <security/tpm/tspi.h>
#include <cpu/intel/romstage.h>
static inline void reset_system(void)
@@ -157,6 +156,4 @@ void romstage_common(const struct romstage_params *params)
romstage_handoff_init(wake_from_s3);
post_code(0x3f);
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(wake_from_s3);
}
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 0320bf5724..51f9a75373 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -37,7 +37,6 @@
#include <stage_cache.h>
#include <string.h>
#include <timestamp.h>
-#include <security/tpm/tspi.h>
#include <vendorcode/google/chromeos/chromeos.h>
asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
@@ -167,15 +166,6 @@ void romstage_common(struct romstage_params *params)
if (romstage_handoff_init(
params->power_state->prev_sleep_state == ACPI_S3) < 0)
hard_reset();
-
- /*
- * Initialize the TPM, unless the TPM was already initialized
- * in verstage and used to verify romstage.
- */
- if ((IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) &&
- !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
- tpm_setup(params->power_state->prev_sleep_state ==
- ACPI_S3);
}
void after_cache_as_ram_stage(void)
diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig
new file mode 100644
index 0000000000..8508210fc6
--- /dev/null
+++ b/src/drivers/tpm/Kconfig
@@ -0,0 +1,7 @@
+config TPM_INIT
+ bool
+ default y if TPM1 || TPM2
+ depends on !VBOOT
+ help
+ This driver automatically initializes the TPM if vboot is not used.
+ The TPM driver init is done during the ramstage chip init phase.
diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc
new file mode 100644
index 0000000000..4e80600ddf
--- /dev/null
+++ b/src/drivers/tpm/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_TPM_INIT) += tpm.c
diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c
new file mode 100644
index 0000000000..e4a81c3da4
--- /dev/null
+++ b/src/drivers/tpm/tpm.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Facebook Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <stddef.h>
+#include <bootstate.h>
+#include <security/tpm/tspi.h>
+
+#if IS_ENABLED(CONFIG_ARCH_X86)
+#include <arch/acpi.h>
+#endif
+
+static void init_tpm_dev(void *unused)
+{
+#if IS_ENABLED(CONFIG_ARCH_X86)
+ int s3resume = acpi_is_wakeup_s3();
+ tpm_setup(s3resume);
+#else
+ tpm_setup(false);
+#endif
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, init_tpm_dev, NULL);
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 6188fccb36..95fe630b9c 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -46,7 +46,6 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include <security/tpm/tspi.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -624,9 +623,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707);
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);
-
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(s3resume);
}
/**
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index d9f00f4bc3..d7bf7c1b63 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -35,7 +35,6 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
-#include <security/tpm/tspi.h>
#include <cbfs.h>
#include <southbridge/intel/bd82x6x/chip.h>
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 6163c35e02..782d6e5654 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -35,7 +35,6 @@
#include <cpu/x86/msr.h>
#include <halt.h>
#include <cbfs.h>
-#include <security/tpm/tspi.h>
#include "ec/compal/ene932/ec.h"
void pch_enable_lpc(void)
diff --git a/src/mainboard/google/rotor/Kconfig b/src/mainboard/google/rotor/Kconfig
index 7a864937d5..437fa02c18 100644
--- a/src/mainboard/google/rotor/Kconfig
+++ b/src/mainboard/google/rotor/Kconfig
@@ -20,8 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOC_MARVELL_MVMAP2315
select MAINBOARD_HAS_CHROMEOS
select BOARD_ROMSIZE_KB_4096
- select MAINBOARD_HAS_I2C_TPM_GENERIC
- select MAINBOARD_HAS_TPM1
config VBOOT
select VBOOT_MOCK_SECDATA
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 36ebcf7d36..f64e0120bd 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -35,7 +35,6 @@
#include <cpu/x86/msr.h>
#include <halt.h>
#include <bootmode.h>
-#include <security/tpm/tspi.h>
#include <cbfs.h>
#include <ec/quanta/it8518/ec.h>
#include "ec.h"
diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig
index 2c4431c829..3d415c4a3e 100644
--- a/src/mainboard/google/urara/Kconfig
+++ b/src/mainboard/google/urara/Kconfig
@@ -24,8 +24,6 @@ config BOARD_SPECIFIC_OPTIONS
select CPU_IMGTEC_PISTACHIO
select COMMON_CBFS_SPI_WRAPPER
select SPI_FLASH
- select MAINBOARD_HAS_I2C_TPM_GENERIC
- select MAINBOARD_HAS_TPM1
config MAINBOARD_DIR
string
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 9f46fe24e6..bdda191069 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -35,7 +35,6 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
-#include <security/tpm/tspi.h>
#define SIO_PORT 0x164e
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index d93cb8c00e..d4c60dd521 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -35,7 +35,6 @@
#include <timestamp.h>
#include <arch/acpi.h>
#include <cbmem.h>
-#include <security/tpm/tspi.h>
#include "dock.h"
#include "arch/early_variables.h"
@@ -282,7 +281,4 @@ void mainboard_romstage_entry(unsigned long bist)
if (!s3resume)
quick_ram_check();
-
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(s3resume);
}
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index 7ea89b8747..e35afc08d6 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -33,7 +33,6 @@
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <Fch/Fch.h>
-#include <security/tpm/tspi.h>
#include "gpio_ftns.h"
@@ -103,9 +102,6 @@ void agesa_postcar(struct sysinfo *cb)
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(false);
-
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
}
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index cea206a02b..3f655da936 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -28,7 +28,6 @@
#include <cbmem.h>
#include <console/console.h>
#include <bootmode.h>
-#include <security/tpm/tspi.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index f502cc393f..ffaff42b72 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -37,7 +37,6 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
-#include <security/tpm/tspi.h>
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
#include <superio/smsc/lpc47n207/lpc47n207.h>
#endif
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 3bfefb9fc7..3e128cdff3 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -28,7 +28,6 @@
#include <device/pci_def.h>
#include <device/device.h>
#include <halt.h>
-#include <security/tpm/tspi.h>
#include <northbridge/intel/sandybridge/chip.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
@@ -117,8 +116,5 @@ void mainboard_romstage_entry(unsigned long bist)
northbridge_romstage_finalize(s3resume);
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(s3resume);
-
post_code(0x3f);
}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index c971b353df..027e0d8edc 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -30,7 +30,6 @@
#include <stage_cache.h>
#include <string.h>
#include <timestamp.h>
-#include <security/tpm/tspi.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
@@ -228,9 +227,6 @@ void romstage_common(struct romstage_params *params)
timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(prev_sleep_state == ACPI_S3);
-
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(prev_sleep_state == ACPI_S3);
}
void asmlinkage romstage_after_car(void)
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 2fbe406fef..f485dfdfea 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -43,7 +43,6 @@
#include <soc/romstage.h>
#include <soc/smm.h>
#include <soc/spi.h>
-#include <security/tpm/tspi.h>
void program_base_addresses(void)
{
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 1e2aa22271..142f3b3375 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -26,7 +26,6 @@
#include <cbmem.h>
#include <cpu/x86/mtrr.h>
#include <elog.h>
-#include <security/tpm/tspi.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <stage_cache.h>
@@ -110,9 +109,6 @@ void romstage_common(struct romstage_params *params)
timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3);
-
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(params->power_state->prev_sleep_state == ACPI_S3);
}
asmlinkage void romstage_after_car(void)
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-01 03:14:12 +0000