diff options
| -rw-r--r-- | src/cpu/amd/model_10xxx/init_cpus.c | 438 | ||||
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c | 58 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/raminit_amdmct.c | 39 | ||||
| -rw-r--r-- | src/northbridge/amd/amdht/AsPsDefs.h | 10 | ||||
| -rw-r--r-- | src/northbridge/amd/amdht/ht_wrapper.c | 23 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/amddefs.h | 84 |
6 files changed, 540 insertions, 112 deletions
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 819f9b1666..5c17a9a118 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "defaults.h" //it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID #ifndef FAM10_SET_FIDVID @@ -29,7 +30,6 @@ #define FAM10_SET_FIDVID_CORE0_ONLY 0 #endif - static inline void print_initcpu8 (const char *strval, u8 val) { printk_debug("%s%02x\n", strval, val); @@ -55,6 +55,7 @@ static inline void print_initcpu(const char *strval, u32 val) static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); +void cpuSetAMDMSR(void); #if PCI_IO_CFG_EXT == 1 static inline void set_EnableCf8ExtCfg(void) @@ -261,12 +262,6 @@ static void wait_ap_started(u32 ap_apicid, void *gp ) } -static void wait_all_aps_started(u32 bsp_apicid) -{ - for_each_ap(bsp_apicid, 0 , wait_ap_started, (void *)0); -} - - static void wait_all_other_cores_started(u32 bsp_apicid) { // all aps other than core0 @@ -287,6 +282,15 @@ static void allow_all_aps_stop(u32 bsp_apicid) lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x14); } +static void enable_apic_ext_id(u32 node) +{ + u32 val; + + val = pci_read_config32(NODE_HT(node), 0x68); + val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); + pci_write_config32(NODE_HT(node), 0x68, val); +} + static void STOP_CAR_AND_CPU() { @@ -383,6 +387,13 @@ static u32 init_cpus(u32 cpu_init_detectedx) if(apicid != bsp_apicid) { + /* Setup each AP's cores MSRs. + * This happens after HTinit. + * The BSP runs this code in it's own path. + */ + cpuSetAMDMSR(); + + #if FAM10_SET_FIDVID == 1 #if (CONFIG_LOGICAL_CPUS == 1) && (FAM10_SET_FIDVID_CORE0_ONLY == 1) // Run on all AP for proper FID/VID setup. @@ -512,13 +523,415 @@ static void setup_remote_node(u8 node) } printk_debug(" done\n"); } -#endif +#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ + +void AMD_Errata281(u8 node, u32 revision, u32 platform) +{ + /* Workaround for Transaction Scheduling Conflict in + * Northbridge Cross Bar. Implement XCS Token adjustment + * for ganged links. Also, perform fix up for the mixed + * revision case. + */ + + u32 reg, val; + u8 i; + u8 mixed = 0; + u8 nodes = get_nodes(); + + if (platform & AMD_PTYPE_SVR) { + /* For each node we need to check for a "broken" node */ + if (!(revision & (AMD_DR_B0 | AMD_DR_B1))) { + for (i = 0; i < nodes; i++) { + if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1)) { + mixed = 1; + break; + } + } + } + + if ((revision & (AMD_DR_B0 | AMD_DR_B1)) || mixed) { + + /* F0X68[22:21] DsNpReqLmt0 = 01b */ + val = pci_read_config32(NODE_PCI(node, 0), 0x68); + val &= ~0x00600000; + val |= 0x00200000; + pci_write_config32(NODE_PCI(node, 0), 0x68, val); + + /* F3X6C */ + val = pci_read_config32(NODE_PCI(node, 3), 0x6C); + val &= ~0x700780F7; + val |= 0x00010094; + pci_write_config32(NODE_PCI(node, 3), 0x6C, val); + + /* F3X7C */ + val = pci_read_config32(NODE_PCI(node, 3), 0x7C); + val &= ~0x707FFF1F; + val |= 0x00144514; + pci_write_config32(NODE_PCI(node, 3), 0x7C, val); + + /* F3X144[3:0] RspTok = 0001b */ + val = pci_read_config32(NODE_PCI(node, 3), 0x144); + val &= ~0x0000000F; + val |= 0x00000001; + pci_write_config32(NODE_PCI(node, 3), 0x144, val); + + for (i = 0; i < 3; i++) { + reg = 0x148 + (i * 4); + val = pci_read_config32(NODE_PCI(node, 3), reg); + val &= ~0x000000FF; + val |= 0x000000DB; + pci_write_config32(NODE_PCI(node, 3), reg, val); + } + } + } +} + + +void AMD_Errata298(void) +{ + /* Workaround for L2 Eviction May Occur during operation to + * set Accessed or dirty bit. + */ + + msr_t msr; + u8 i; + u8 affectedRev = 0; + u8 nodes = get_nodes(); + + /* For each core we need to check for a "broken" node */ + for (i = 0; i < nodes; i++) { + if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2)) { + affectedRev = 1; + break; + } + } + + if (affectedRev) { + msr = rdmsr(HWCR); + msr.lo |= 0x08; /* Set TlbCacheDis bit[3] */ + wrmsr(HWCR, msr); + + msr = rdmsr(BU_CFG); + msr.lo |= 0x02; /* Set TlbForceMemTypeUc bit[1] */ + wrmsr(BU_CFG, msr); + + msr = rdmsr(OSVW_ID_Length); + msr.lo |= 0x01; /* OS Visible Workaround - MSR */ + wrmsr(OSVW_ID_Length, msr); + + msr = rdmsr(OSVW_Status); + msr.lo |= 0x01; /* OS Visible Workaround - MSR */ + wrmsr(OSVW_Status, msr); + } + + if (!affectedRev && (mctGetLogicalCPUID(0xFF) & AMD_DR_B3)) { + msr = rdmsr(OSVW_ID_Length); + msr.lo |= 0x01; /* OS Visible Workaround - MSR */ + wrmsr(OSVW_ID_Length, msr); + + } +} + + +u32 get_platform_type(void) +{ + u32 ret = 0; + + switch(SYSTEM_TYPE) { + case 1: + ret |= AMD_PTYPE_DSK; + break; + case 2: + ret |= AMD_PTYPE_MOB; + break; + case 0: + ret |= AMD_PTYPE_SVR; + break; + default: + break; + } + + /* FIXME: add UMA support. */ + + /* All Fam10 are multi core */ + ret |= AMD_PTYPE_MC; + + return ret; +} + + +/** + * AMD_CpuFindCapability - Traverse PCI capability list to find host HT links. + * HT Phy operations are not valid on links that aren't present, so this + * prevents invalid accesses. + * + * Returns the offset of the link register. + */ +BOOL AMD_CpuFindCapability (u8 node, u8 cap_count, u8 *offset) +{ + u32 val; + + /* get start of CPU HT Host Capabilities */ + val = pci_read_config32(NODE_PCI(node, 0), 0x34); + val &= 0xFF; + + cap_count++; + + /* Traverse through the capabilities. */ + do { + val = pci_read_config32(NODE_PCI(node, 0), val); + /* Is the capability block a HyperTransport capability block? */ + if ((val & 0xFF) == 0x08) + /* Is the HT capability block an HT Host Capability? */ + if ((val & 0xE0000000) == (1 << 29)) + cap_count--; + val = (val >> 8) & 0xFF; + } while (cap_count && val); + + *offset = (u8) val; + + /* If requested capability found val != 0 */ + if (!cap_count) + return TRUE; + else + return FALSE; +} + + +/** + * AMD_checkLinkType - Compare desired link characteristics using a logical + * link type mask. + * + * Returns the link characteristic mask. + */ +u32 AMD_checkLinkType (u8 node, u8 link, u8 regoff) +{ + u32 val; + u32 linktype; + + /* Check coherency */ + val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x18); + val &= 0x1F; + + if (val == 3) + linktype |= HTPHY_LINKTYPE_COHERENT; + + if (val == 7) + linktype |= HTPHY_LINKTYPE_NONCOHERENT; + + /* Check gen3 */ + val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08); + + if (((val >> 8) & 0x0F) > 6) + linktype |= HTPHY_LINKTYPE_HT3; + else + linktype |= HTPHY_LINKTYPE_HT1; + + + /* Check ganged */ + val = pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170); + + if ( val & 1) + linktype |= HTPHY_LINKTYPE_GANGED; + else + linktype |= HTPHY_LINKTYPE_UNGANGED; + + return linktype; +} + + +/** + * AMD_SetHtPhyRegister - Use the HT link's HT Phy portal registers to update + * a phy setting for that link. + */ +void AMD_SetHtPhyRegister (u8 node, u8 link, u8 entry) +{ + u32 phyReg; + u32 phyBase; + u32 val; + + /* Determine this link's portal */ + if (link > 3) + link -= 4; + + phyBase = ((u32)link << 3) | 0x180; + + + /* Get the portal control register's initial value + * and update it to access the desired phy register + */ + phyReg = pci_read_config32(NODE_PCI(node, 4), phyBase); + + if (fam10_htphy_default[entry].htreg > 0x1FF) { + phyReg &= ~HTPHY_DIRECT_OFFSET_MASK; + phyReg |= HTPHY_DIRECT_MAP; + } else { + phyReg &= ~HTPHY_OFFSET_MASK; + } + + /* Now get the current phy register data + * LinkPhyDone = 0, LinkPhyWrite = 0 is a read + */ + phyReg |= fam10_htphy_default[entry].htreg; + pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg); + + do { + val = pci_read_config32(NODE_PCI(node, 4), phyBase); + } while (!(val & HTPHY_IS_COMPLETE_MASK)); + + /* Now we have the phy register data, apply the change */ + val = pci_read_config32(NODE_PCI(node, 4), phyBase + 4); + val &= ~fam10_htphy_default[entry].mask; + val |= fam10_htphy_default[entry].data; + pci_write_config32(NODE_PCI(node, 4), phyBase + 4, val); + + /* write it through the portal to the phy + * LinkPhyDone = 0, LinkPhyWrite = 1 is a write + */ + phyReg |= HTPHY_WRITE_CMD; + pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg); + + do { + val = pci_read_config32(NODE_PCI(node, 4), phyBase); + } while (!(val & HTPHY_IS_COMPLETE_MASK)); +} + + +void cpuSetAMDMSR(void) +{ + /* This routine loads the CPU with default settings in fam10_msr_default + * table . It must be run after Cache-As-RAM has been enabled, and + * Hypertransport initialization has taken place. Also note + * that it is run on the current processor only, and only for the current + * processor core. + */ + msr_t msr; + u8 i; + u32 revision, platform; + + printk_debug("cpuSetAMDMSR "); + + revision = mctGetLogicalCPUID(0xFF); + platform = get_platform_type(); + + for(i = 0; i < sizeof(fam10_msr_default)/sizeof(fam10_msr_default[0]); i++) { + if ((fam10_msr_default[i].revision & revision) && + (fam10_msr_default[i].platform & platform)) { + msr = rdmsr(fam10_msr_default[i].msr); + msr.hi &= ~fam10_msr_default[i].mask_hi; + msr.hi |= fam10_msr_default[i].data_hi; + msr.lo &= ~fam10_msr_default[i].mask_lo; + msr.lo |= fam10_msr_default[i].data_lo; + wrmsr(fam10_msr_default[i].msr, msr); + } + } + AMD_Errata298(); + + printk_debug(" done\n"); +} + + +void cpuSetAMDPCI(u8 node) +{ + /* This routine loads the CPU with default settings in fam10_pci_default + * table . It must be run after Cache-As-RAM has been enabled, and + * Hypertransport initialization has taken place. Also note + * that it is run for the first core on each node + */ + u8 i, j; + u32 revision, platform; + u32 val; + u8 offset; + + printk_debug("cpuSetAMDPCI %02d", node); + + revision = mctGetLogicalCPUID(node); + platform = get_platform_type(); + + for(i = 0; i < sizeof(fam10_pci_default)/sizeof(fam10_pci_default[0]); i++) { + if ((fam10_pci_default[i].revision & revision) && + (fam10_pci_default[i].platform & platform)) { + val = pci_read_config32(NODE_PCI(node, + fam10_pci_default[i].function), + fam10_pci_default[i].offset); + val &= ~fam10_pci_default[i].mask; + val |= fam10_pci_default[i].data; + pci_write_config32(NODE_PCI(node, + fam10_pci_default[i].function), + fam10_pci_default[i].offset, val); + } + } + + for(i = 0; i < sizeof(fam10_htphy_default)/sizeof(fam10_htphy_default[0]); i++) { + if ((fam10_htphy_default[i].revision & revision) && + (fam10_htphy_default[i].platform & platform)) { + /* HT Phy settings either apply to both sublinks or have + * separate registers for sublink zero and one, so there + * will be two table entries. So, here we only loop + cd t * through the sublink zeros in function zero. + */ + for (j = 0; j < 4; j++) { + if (AMD_CpuFindCapability(node, j, &offset)) { + if (AMD_checkLinkType(node, j, offset) + & fam10_htphy_default[i].linktype) { + AMD_SetHtPhyRegister(node, j, i); + } + } else { + /* No more capabilities, + * link not present + */ + break; + } + } + } + } + + /* FIXME: add UMA support and programXbarToSriReg(); */ + + AMD_Errata281(node, revision, platform); + + /* FIXME: if the dct phy doesn't init correct it needs to reset. + if (revision & (AMD_DR_B2 | AMD_DR_B3)) + dctPhyDiag(); */ + + printk_debug(" done\n"); +} + + +void cpuInitializeMCA(void) +{ + /* Clears Machine Check Architecture (MCA) registers, which power on + * containing unknown data, on currently running processor. + * This routine should only be executed on initial power on (cold boot), + * not across a warm reset because valid data is present at that time. + */ + + msr_t msr; + u32 reg; + u8 i; + + if (cpuid_edx(1) & 0x4080) { /* MCE and MCA (edx[7] and edx[14]) */ + msr = rdmsr(MCG_CAP); + if (msr.lo & MCG_CTL_P){ /* MCG_CTL_P bit is set? */ + msr.lo &= 0xFF; + msr.lo--; + msr.lo <<= 2; /* multiply the count by 4 */ + reg = MC0_STA + msr.lo; + msr.lo = msr.hi = 0; + for (i=0; i < 4; i++) { + wrmsr (reg, msr); + reg -=4; /* Touch status regs for each bank */ + } + } + } +} + + /** * finalize_node_setup() * * Do any additional post HT init * - * This could really be moved to cache_as_ram_auto.c since it really isn't HT init. */ void finalize_node_setup(struct sys_info *sysinfo) { @@ -535,7 +948,10 @@ void finalize_node_setup(struct sys_info *sysinfo) sysinfo->sbdn = get_sbdn(sysinfo->sbbusn); #endif - setup_link_trans_cntrl(); + + for (i = 0; i < nodes; i++) { + cpuSetAMDPCI(i); + } #if FAM10_SET_FIDVID == 1 // Prep each node for FID/VID setup. diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c index cebdcb6836..5ee60cadcf 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -255,60 +255,30 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk_debug("Family_Model: %08x \n", val); - - /* FIXME: Need to make sure that APs are updated with the microcode and Errata */ - update_microcode(val); - post_code(0x33); - - /* FIXME: This errata code needs to move out of the mainboard but I am not sure where to yet.*/ - /* FIXME: Check CPU revision to apply correct erratas */ - /* Rev B errata */ - /* Errata #169 - supercedes errata #131 */ - msr = rdmsr(0xC001001F); - msr.hi |= 1 << (32 - 32); - wrmsr(0xC001101F, msr); - - /* Errata #202 [DIS_PIGGY_BACK_SCRUB]=1 */ - msr = rdmsr(0xC0011022); - msr.hi |= 1 << 24; - wrmsr(0xC0010022, msr); - - /* 298 : FIXME: Fixed in B3/C1 */ -/* msr = rdmsr(0xC0010015); - msr.lo |= 1 << 3; - wrmsr(0xC0010015, msr); - - msr = rdmsr(0xC0011023); - msr.lo |= 1 << 1; - wrmsr(0xC0010023, msr); -*/ - /* FIXME: Erratum #254 revB1 BU_CFG[21]=1 */ - - + printk_debug("BSP Family_Model: %08x \n", val); printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n"); - setup_mb_resource_map(); - post_code(0x34); - -// dump_pci_device(PCI_DEV(CBB, CDB, 0)); - printk_debug("bsp_apicid = %02x \n", bsp_apicid); printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); - post_code(0x35); + update_microcode(val); + post_code(0x33); - // FIXME: Add needs_reset check to HT links. - amd_ht_init(sysinfo); -// print_pci_devices(); -// dump_pci_devices(); + cpuSetAMDMSR(); + post_code(0x34); - post_code(0x36); + amd_ht_init(sysinfo); + post_code(0x35); + /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x36); + /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. It would be nice to fixup prink spinlocks for ROM XIP mode. @@ -378,10 +348,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); + post_code(0x40); // die("Die Before MCT init."); - post_code(0x40); printk_debug("raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 72d8469737..9696689281 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -106,23 +106,26 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) u32 mctGetLogicalCPUID(u32 Node) { + /* FIXME: Move this to a more generic place. Maybe to the CPU code */ + /* Converts the CPUID to a logical ID MASK that is used to check + CPU version support versions */ u32 dev; u32 val, valx; u32 family, model, stepping; u32 ret; - dev = PA_NBMISC(Node); - val = Get_NB32(dev, 0xfc); - print_debug("Family_Model:"); print_debug_hex32(val); print_debug("\n"); - family = ((val >> 8) & 0x0f) + ((val>>20) & 0xff); - model = ((val>>4) & 0x0f) | ((val>>(16-4)) & 0xf0); - stepping = val & 0xff; - print_debug("Family:"); print_debug_hex8(family); print_debug("\t"); - print_debug("Model:"); print_debug_hex8(model); print_debug("\t"); - print_debug("Stepping:"); print_debug_hex8(stepping); print_debug("\n"); + if (Node == 0xFF) { /* current node */ + val = cpuid_eax(0x80000001); + } else { + dev = PA_NBMISC(Node); + val = Get_NB32(dev, 0xfc); + } + + family = ((val >> 8) & 0x0f) + ((val >> 20) & 0xff); + model = ((val >> 4) & 0x0f) | ((val >> (16-4)) & 0xf0); + stepping = val & 0x0f; - valx = (family<<12) | (model<<4) | (stepping); - print_debug("converted:"); print_debug_hex32(valx); print_debug("\n"); + valx = (family << 12) | (model << 4) | (stepping); switch (valx) { case 0x10000: @@ -134,7 +137,21 @@ u32 mctGetLogicalCPUID(u32 Node) case 0x10002: ret = AMD_DR_A2; break; + case 0x10020: + ret = AMD_DR_B0; + break; + case 0x10021: + ret = AMD_DR_B1; + break; + case 0x10022: + ret = AMD_DR_B2; + break; + case 0x10023: + ret = AMD_DR_B3; + break; default: + /* FIXME: mabe we should die() here. */ + print_err("FIXME! CPU Version unknown or not supported! \n"); ret = 0; } diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index 86d3375f07..62b7edba6d 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,14 +21,6 @@ #ifndef ASPSDEFS_H #define ASPSDEFS_H -/* AMD Platform Types */ -#define AMD_PTYPE_DSK 1 -#define AMD_PTYPE_MOB 2 -#define AMD_PTYPE_SVR 4 -#define AMD_PTYPE_DC 8 -#define AMD_PTYPE_MC 0x10 -#define AMD_PTYPE_UMA 0x20 - #define APIC_BAR 0x1b /* APIC_BAR register */ #define APIC_BAR_BP 0x100 /* APIC_BAR BSP bit */ diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index aaf67a47a7..ad276e42ef 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -60,6 +60,7 @@ #define NODE_MP(x) NODE_PCI(x,1) #define NODE_MC(x) NODE_PCI(x,3) #define NODE_LC(x) NODE_PCI(x,4) + static u32 get_nodes(void) { device_t dev; @@ -75,26 +76,6 @@ static u32 get_nodes(void) return nodes; } -static void enable_apic_ext_id(u32 node) -{ - u32 val; - val = pci_read_config32(NODE_HT(node), 0x68); - val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); - pci_write_config32(NODE_HT(node), 0x68, val); -} - - -static void setup_link_trans_cntrl() -{ - /* FIXME: Not sure that this belongs here but it is HT related */ - u32 val; - val = pci_read_config32(NODE_HT(0), 0x68); - val |= 0x00206800; // DSNpReqLimit, LimitCldtCfg, BufRefPri, RespPassPW per BKDG; - pci_write_config32(NODE_HT(0), 0x68, val); -} - - - /** * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index d2ba49790f..127173827e 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* FIXME: this file should be moved to include/cpu/amd/amddefs.h */ + /* Public Revisions - USE THESE VERSIONS TO MAKE COMPARE WITH CPULOGICALID RETURN VALUE*/ #define AMD_SAFEMODE 0x80000000 /* Unknown future revision - SAFE MODE */ #define AMD_NPT_F0 0x00000001 /* F0 stepping */ @@ -37,33 +39,83 @@ #define AMD_DR_B1 0x00100000 /* Barcelona B1 */ #define AMD_DR_B2 0x00200000 /* Barcelona B2 */ #define AMD_DR_BA 0x00400000 /* Barcelona BA */ +#define AMD_DR_B3 0x00800000 /* Barcelona B3 */ /* - Groups - Create as many as you wish, from the above public values -*/ -#define AMD_NPT_F2 (AMD_NPT_F2C + AMD_NPT_F2D + AMD_NPT_F2E + AMD_NPT_F2G + AMD_NPT_F2J + AMD_NPT_F2K) + * Groups - Create as many as you wish, from the above public values + */ +#define AMD_NPT_F2 (AMD_NPT_F2C | AMD_NPT_F2D | AMD_NPT_F2E | AMD_NPT_F2G | AMD_NPT_F2J | AMD_NPT_F2K) #define AMD_NPT_F3 (AMD_NPT_F3L) -#define AMD_NPT_Fx (AMD_NPT_F0 + AMD_NPT_F1 + AMD_NPT_F2 + AMD_NPT_F3) -#define AMD_NPT_Gx (AMD_NPT_G0A + AMD_NPT_G1B) -#define AMD_NPT_ALL (AMD_NPT_Fx + AMD_NPT_Gx) -#define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2) -#define AMD_FINEDELAY (AMD_NPT_F0 + AMD_NPT_F1 + AMD_NPT_F2) +#define AMD_NPT_Fx (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2 | AMD_NPT_F3) +#define AMD_NPT_Gx (AMD_NPT_G0A | AMD_NPT_G1B) +#define AMD_NPT_ALL (AMD_NPT_Fx | AMD_NPT_Gx) +#define AMD_FINEDELAY (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2) #define AMD_GT_F0 (AMD_NPT_ALL AND NOT AMD_NPT_F0) +#define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2) +#define AMD_DR_Bx (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA) +#define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) +#define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) +#define AMD_DR_ALL (AMD_DR_Bx) +/* + * Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE + */ +#define AMD_PTYPE_DSK 0x001 /* Desktop/DTR/UP */ +#define AMD_PTYPE_MOB 0x002 /* Mobile/Cool-n-quiet */ +#define AMD_PTYPE_SVR 0x004 /* Workstation/Server/Multicore DT */ +#define AMD_PTYPE_UC 0x008 /* Single Core */ +#define AMD_PTYPE_DC 0x010 /* Dual Core */ +#define AMD_PTYPE_MC 0x020 /* Multi Core (>2) */ +#define AMD_PTYPE_UMA 0x040 /* UMA required */ -#define CPUID_EXT_PM 0x80000007 - -#define CPUID_MODEL 1 + /* + * Groups - Create as many as you wish, from the above public values + */ +#define AMD_PTYPE_ALL 0xFFFFFFFF /* A mask for all */ -#define HWCR 0xC0010015 +/* + * CPU PCI HT PHY REGISTER, LINK TYPES - PRIVATE + */ +#define HTPHY_LINKTYPE_HT3 0x00000001 +#define HTPHY_LINKTYPE_HT1 0x00000002 +#define HTPHY_LINKTYPE_COHERENT 0x00000004 +#define HTPHY_LINKTYPE_NONCOHERENT 0x00000008 +#define HTPHY_LINKTYPE_CONNECTED (HTPHY_LINKTYPE_COHERENT | HTPHY_LINKTYPE_NONCOHERENT) +#define HTPHY_LINKTYPE_GANGED 0x00000010 +#define HTPHY_LINKTYPE_UNGANGED 0x00000020 +#define HTPHY_LINKTYPE_ALL 0x7FFFFFFF -#define FidVidStatus 0xC0010042 +/* + * CPU HT PHY REGISTERS, FIELDS, AND MASKS + */ +#define HTPHY_OFFSET_MASK 0xE00001FF +#define HTPHY_WRITE_CMD 0x40000000 +#define HTPHY_IS_COMPLETE_MASK 0x80000000 +#define HTPHY_DIRECT_MAP 0x20000000 +#define HTPHY_DIRECT_OFFSET_MASK 0xE000FFFF +/* + * Various AMD MSRs + */ +#define CPUID_EXT_PM 0x80000007 +#define CPUID_MODEL 1 +#define MCG_CAP 0x00000179 + #define MCG_CTL_P 8 +#define MC0_CTL 0x00000400 +#define MC0_STA MC0_CTL + 1 #define FS_Base 0xC0000100 - - +#define SYSCFG 0xC0010010 +#define HWCR 0xC0010015 +#define NB_CFG 0xC001001F +#define FidVidStatus 0xC0010042 +#define MC4_CTL_MASK 0xC0010048 +#define OSVW_ID_Length 0xC0010140 +#define OSVW_Status 0xC0010141 +#define CPUIDFEATURES 0xC0011004 +#define LS_CFG 0xC0011020 +#define DC_CFG 0xC0011022 #define BU_CFG 0xC0011023 #define BU_CFG2 0xC001102A |