diff options
| -rw-r--r-- | src/mainboard/google/veyron_brain/romstage.c | 25 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_danger/romstage.c | 25 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_jerry/romstage.c | 25 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_mickey/romstage.c | 25 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_mighty/romstage.c | 25 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_minnie/romstage.c | 25 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_pinky/romstage.c | 25 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_rialto/romstage.c | 25 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_romy/romstage.c | 25 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_shark/romstage.c | 25 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_speedy/romstage.c | 25 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/bootblock.c | 3 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/include/soc/memlayout.ld | 1 |
14 files changed, 71 insertions, 209 deletions
diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c index 9f7b1a5de8..f243235d7b 100644 --- a/src/mainboard/google/veyron_brain/romstage.c +++ b/src/mainboard/google/veyron_brain/romstage.c @@ -79,13 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -93,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -109,13 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c index 80d9081fed..e9857b8e0b 100644 --- a/src/mainboard/google/veyron_danger/romstage.c +++ b/src/mainboard/google/veyron_danger/romstage.c @@ -80,13 +80,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -97,13 +91,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -113,13 +106,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index e509a4aec5..5ccbe3ec23 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -85,13 +85,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -102,13 +96,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -118,13 +111,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index 9f7b1a5de8..f243235d7b 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -79,13 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -93,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -109,13 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c index e509a4aec5..5ccbe3ec23 100644 --- a/src/mainboard/google/veyron_mighty/romstage.c +++ b/src/mainboard/google/veyron_mighty/romstage.c @@ -85,13 +85,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -102,13 +96,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -118,13 +111,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_minnie/romstage.c b/src/mainboard/google/veyron_minnie/romstage.c index 68ab661d44..9cdacc3e1a 100644 --- a/src/mainboard/google/veyron_minnie/romstage.c +++ b/src/mainboard/google/veyron_minnie/romstage.c @@ -86,13 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -103,13 +97,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -119,13 +112,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index b536391249..3792e6273a 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -93,13 +93,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -110,13 +104,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -126,13 +119,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index 68ab661d44..9cdacc3e1a 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -86,13 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -103,13 +97,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -119,13 +112,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c index 9f7b1a5de8..f243235d7b 100644 --- a/src/mainboard/google/veyron_romy/romstage.c +++ b/src/mainboard/google/veyron_romy/romstage.c @@ -79,13 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -93,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -109,13 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_shark/romstage.c b/src/mainboard/google/veyron_shark/romstage.c index 68ab661d44..9cdacc3e1a 100644 --- a/src/mainboard/google/veyron_shark/romstage.c +++ b/src/mainboard/google/veyron_shark/romstage.c @@ -86,13 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -103,13 +97,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -119,13 +112,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c index 68ab661d44..9cdacc3e1a 100644 --- a/src/mainboard/google/veyron_speedy/romstage.c +++ b/src/mainboard/google/veyron_speedy/romstage.c @@ -86,13 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -103,13 +97,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -119,13 +112,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 3a4712e4d3..1800b16f26 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -24,6 +24,7 @@ config SOC_ROCKCHIP_RK3288 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 + select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select HAVE_UART_SPECIAL diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index d60c860054..43776521f4 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -26,9 +26,12 @@ #include <soc/grf.h> #include <soc/timer.h> #include <symbols.h> +#include <timestamp.h> void bootblock_soc_init(void) { + timestamp_init(timestamp_get()); + rkclk_init(); mmu_init(); diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index cd484c8594..0b759327de 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -41,6 +41,7 @@ SECTIONS OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 41K) TTB_SUBTABLES(0xFF716C00, 1K) PRERAM_CBFS_CACHE(0xFF717000, 1K) + TIMESTAMP(0xFF717400, 0x180) STACK(0xFF717580, 3K - 0x180) SRAM_END(0xFF718000) |