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-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/ramstage.h6
-rw-r--r--src/drivers/intel/fsp1_1/ramstage.c8
2 files changed, 1 insertions, 13 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
index 0a6295edc5..f925088e00 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
@@ -6,12 +6,6 @@
#include <fsp/util.h>
#include <stdint.h>
-/*
- * Load FSP from stage cache or CBFS. This allows SoCs to load FSP separately
- * from calling silicon init. It might be required in cases where stage cache is
- * no longer available by the point SoC calls into silicon init.
- */
-void fsp_load(void);
/* Perform Intel silicon init. */
void intel_silicon_init(void);
void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup);
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index eb226dbb65..5fff60ac1a 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -173,15 +173,11 @@ static int fsp_find_and_relocate(struct prog *fsp)
return 0;
}
-void fsp_load(void)
+static void fsp_load(void)
{
- static int load_done;
struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
int is_s3_wakeup = acpi_is_wakeup_s3();
- if (load_done)
- return;
-
if (is_s3_wakeup && !CONFIG(NO_STAGE_CACHE)) {
printk(BIOS_DEBUG, "FSP: Loading binary from cache\n");
stage_cache_load_stage(STAGE_REFCODE, &fsp);
@@ -192,8 +188,6 @@ void fsp_load(void)
/* FSP_INFO_HEADER is set as the program entry. */
fsp_update_fih(prog_entry(&fsp));
-
- load_done = 1;
}
void intel_silicon_init(void)