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-rw-r--r--src/mainboard/google/dedede/variants/baseboard/devicetree.cb16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index cdd325cdd6..aedd32f7cc 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -3,6 +3,22 @@ chip soc/intel/tigerlake
device lapic 0 on end
end
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route, i.e., if this route changes then the affected GPE
+ # offset bits also need to be changed.
+ # DW0 is used by:
+ # - GPP_B3 - TRACKPAD_INT_ODL
+ # - GPP_B4 - H1_AP_INT_ODL
+ # DW1 is used by:
+ # - GPP_D3 - WLAN_PCIE_WAKE_ODL
+ # DW2 is used by:
+ # - GPP_H16 - WWAN_HOST_WAKE
+ # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3.
+ register "pmc_gpe0_dw0" = "GPP_B"
+ register "pmc_gpe0_dw1" = "GPP_D"
+ register "pmc_gpe0_dw2" = "GPP_H"
+
device domain 0 on
device pci 00.0 off end # Host Bridge
device pci 02.0 off end # Integrated Graphics Device