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-rw-r--r--src/cpu/amd/pi/00660F01/Kconfig13
-rw-r--r--src/cpu/amd/pi/00660F01/Makefile.inc14
-rw-r--r--src/cpu/amd/pi/00660F01/acpi/cpu.asl48
-rw-r--r--src/cpu/amd/pi/00660F01/chip_name.c7
-rw-r--r--src/cpu/amd/pi/00660F01/fixme.c55
-rw-r--r--src/cpu/amd/pi/00660F01/model_15_init.c119
-rw-r--r--src/cpu/amd/pi/Kconfig2
-rw-r--r--src/cpu/amd/pi/Makefile.inc1
-rw-r--r--src/northbridge/amd/agesa/state_machine.h3
-rw-r--r--src/southbridge/amd/pi/hudson/Kconfig3
-rw-r--r--src/southbridge/amd/pi/hudson/Makefile.inc12
-rw-r--r--src/vendorcode/amd/pi/Kconfig4
-rw-r--r--src/vendorcode/amd/pi/Makefile.inc11
13 files changed, 3 insertions, 289 deletions
diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig
deleted file mode 100644
index 1cdfb1d7be..0000000000
--- a/src/cpu/amd/pi/00660F01/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-config CPU_AMD_PI_00660F01
- bool
- select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_PI_00660F01
-
-config CPU_ADDR_BITS
- int
- default 48
-
-endif
diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc
deleted file mode 100644
index 69635fc1f2..0000000000
--- a/src/cpu/amd/pi/00660F01/Makefile.inc
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-romstage-y += fixme.c
-ramstage-y += fixme.c
-ramstage-y += chip_name.c
-ramstage-y += model_15_init.c
-
-subdirs-y += ../../mtrr
-subdirs-y += ../../../x86/tsc
-subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
-subdirs-y += ../../../x86/pae
-subdirs-y += ../../../x86/smm
diff --git a/src/cpu/amd/pi/00660F01/acpi/cpu.asl b/src/cpu/amd/pi/00660F01/acpi/cpu.asl
deleted file mode 100644
index ede5021e03..0000000000
--- a/src/cpu/amd/pi/00660F01/acpi/cpu.asl
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Processor Object
- *
- */
-Scope (\_SB) { /* define processor scope */
-
- Device (P000) {
- Name(_HID, "ACPI0007")
- Name(_UID, 0)
- }
-
- Device (P001) {
- Name(_HID, "ACPI0007")
- Name(_UID, 1)
- }
-
- Device (P002) {
- Name(_HID, "ACPI0007")
- Name(_UID, 2)
- }
-
- Device (P003) {
- Name(_HID, "ACPI0007")
- Name(_UID, 3)
- }
-
- Device (P004) {
- Name(_HID, "ACPI0007")
- Name(_UID, 4)
- }
-
- Device (P005) {
- Name(_HID, "ACPI0007")
- Name(_UID, 5)
- }
-
- Device (P006) {
- Name(_HID, "ACPI0007")
- Name(_UID, 6)
- }
-
- Device (P007) {
- Name(_HID, "ACPI0007")
- Name(_UID, 7)
- }
-} /* End _SB scope */
diff --git a/src/cpu/amd/pi/00660F01/chip_name.c b/src/cpu/amd/pi/00660F01/chip_name.c
deleted file mode 100644
index 06fa4442ec..0000000000
--- a/src/cpu/amd/pi/00660F01/chip_name.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-
-struct chip_operations cpu_amd_pi_00660F01_ops = {
- CHIP_NAME("AMD CPU Family 15h Model 60h-6Fh")
-};
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
deleted file mode 100644
index 9b208ecc4c..0000000000
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <Porting.h>
-#include <AGESA.h>
-#include <amdlib.h>
-
-void amd_initcpuio(void)
-{
- UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
- AMD_CONFIG_PARAMS StdHeader;
-
- /* Enable legacy video routing: D18F1xF4 VGA Enable */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
- PciData = 1;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
- * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
- * set to non-posted regions.
- */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
- /* last address before processor local APIC at FEE00000 */
- PciData = 0x00FEDF00;
- /* set NP (non-posted) bit */
- PciData |= 1 << 7;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
- /* lowest NP address is HPET at FED00000 */
- PciData = (0xFED00000 >> 8) | 3;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Map the remaining PCI hole as posted MMIO */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
- PciData = 0x00FECF00; /* last address before non-posted range */
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
- MsrReg = (MsrReg >> 8) | 3;
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
- PciData = (UINT32)MsrReg;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Send all IO (0000-FFFF) to southbridge. */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
- PciData = 0x0000F000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
- PciData = 0x00000003;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-}
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
deleted file mode 100644
index 4bb289622c..0000000000
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <cpu/x86/pae.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-
-#include <amdlib.h>
-#include <PspBaseLib.h>
-
-void PSPProgBar3Msr(void *Buffer);
-
-void PSPProgBar3Msr(void *Buffer)
-{
- u32 Bar3Addr;
- u64 Tmp64;
- /* Get Bar3 Addr */
- Bar3Addr = PspLibPciReadPspConfig(0x20);
- Tmp64 = Bar3Addr;
- printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64);
- LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL);
- LibAmdMsrRead(0xC00110A2, &Tmp64, NULL);
-}
-
-static void model_15_init(struct device *dev)
-{
- printk(BIOS_DEBUG, "Model 15 Init.\n");
-
- u8 i;
- msr_t msr;
- int num_banks;
- int msrno;
-#if CONFIG(LOGICAL_CPUS)
- u32 siblings;
-#endif
-
- disable_cache();
- /* Enable access to AMD RdDram and WrDram extension bits */
- msr = rdmsr(SYSCFG_MSR);
- msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
- msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
- wrmsr(SYSCFG_MSR, msr);
-
- // BSP: make a0000-bffff UC, c0000-fffff WB
- msr.lo = msr.hi = 0;
- wrmsr(MTRR_FIX_16K_A0000, msr);
- msr.lo = msr.hi = 0x1e1e1e1e;
- wrmsr(MTRR_FIX_64K_00000, msr);
- wrmsr(MTRR_FIX_16K_80000, msr);
- for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
- wrmsr(msrno, msr);
-
- msr = rdmsr(SYSCFG_MSR);
- msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
- msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
- wrmsr(SYSCFG_MSR, msr);
-
- x86_mtrr_check();
- x86_enable_cache();
-
- /* zero the machine check error status registers */
- msr = rdmsr(IA32_MCG_CAP);
- num_banks = msr.lo & MCA_BANKS_MASK;
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
-
- /* Enable the local CPU APICs */
- setup_lapic();
-
-#if CONFIG(LOGICAL_CPUS)
- siblings = cpuid_ecx(0x80000008) & 0xff;
-
- if (siblings > 0) {
- msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
- msr.lo |= 1 << 28;
- wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
- msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
- msr.hi |= 1 << (33 - 32);
- wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
- }
- printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif
- PSPProgBar3Msr(NULL);
-
- /* DisableCf8ExtCfg */
- msr = rdmsr(NB_CFG_MSR);
- msr.hi &= ~(1 << (46 - 32));
- wrmsr(NB_CFG_MSR, msr);
-
- /* Write protect SMM space with SMMLOCK. */
- msr = rdmsr(HWCR_MSR);
- msr.lo |= (1 << 0);
- wrmsr(HWCR_MSR, msr);
-}
-
-static struct device_operations cpu_dev_ops = {
- .init = model_15_init,
-};
-
-static const struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_AMD, 0x660f00 },
- { X86_VENDOR_AMD, 0x660f01 },
- { 0, 0 },
-};
-
-static const struct cpu_driver model_15 __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
-};
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index e626ef1c74..dff896f016 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -4,7 +4,6 @@ config CPU_AMD_PI
bool
default y if CPU_AMD_PI_00630F01
default y if CPU_AMD_PI_00730F01
- default y if CPU_AMD_PI_00660F01
default n
select ARCH_ALL_STAGES_X86_32
select DRIVERS_AMD_PI
@@ -46,4 +45,3 @@ endif # CPU_AMD_PI
source "src/cpu/amd/pi/00630F01/Kconfig"
source "src/cpu/amd/pi/00730F01/Kconfig"
-source "src/cpu/amd/pi/00660F01/Kconfig"
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index 969434700e..dc9fd6b2bd 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -2,4 +2,3 @@
subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
-subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h
index 93a70cd53f..a857727a0a 100644
--- a/src/northbridge/amd/agesa/state_machine.h
+++ b/src/northbridge/amd/agesa/state_machine.h
@@ -83,9 +83,6 @@ void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume);
void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late);
void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late);
-#if CONFIG(CPU_AMD_PI_00660F01)
-typedef void AMD_S3SAVE_PARAMS;
-#endif
void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save);
/* FCH callouts, not used with CIMx. */
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index 6a1a9c848b..89dcad6086 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -60,7 +60,7 @@ config HUDSON_GEC_FWM
config HUDSON_PSP
bool
- default y if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01
+ default y if CPU_AMD_PI_00730F01
config AMDFW_CONFIG_FILE
string "AMD PSP Firmware config file"
@@ -88,7 +88,6 @@ config AMD_PUBKEY_FILE
depends on HUDSON_PSP
string "AMD public Key"
default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
- default "3rdparty/blobs/southbridge/amd/kern/PSP/AmdPubKeyCZ.bin" if CPU_AMD_PI_00660F01
config HUDSON_SATA_MODE
int "SATA Mode"
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 94c759ee3e..215a5a12bd 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -83,18 +83,6 @@ FIRMWARE_TYPE=
endif
-ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y)
-FIRMWARE_LOCATION=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)))
-FIRMWARE_TYPE=CZ
-
-PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATION)/PspBootLoader_prod_CZ.sbin
-PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATION)/PspRecoveryBootLoader_prod_CZ.sbin
-PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureOs_prod_CZ.csbin
-PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATION)/PspTrustlets_prod_CZ.cbin
-TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/TrustletKey_prod_CZ.sbin
-SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware2_prod_CZ.sbin
-endif
-
#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/RtmPubSigned$(FIRMWARE_TYPE).key
#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATION)/PspNvram$(FIRMWARE_TYPE).bin
#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureDebug$(FIRMWARE_TYPE).Key
diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig
index 15d2ab270d..fb4935bbb0 100644
--- a/src/vendorcode/amd/pi/Kconfig
+++ b/src/vendorcode/amd/pi/Kconfig
@@ -26,7 +26,7 @@
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
-if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE
+if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || SOC_AMD_STONEYRIDGE
config AGESA_BINARY_PI_VENDORCODE_PATH
string "AGESA PI directory path"
@@ -34,7 +34,6 @@ config AGESA_BINARY_PI_VENDORCODE_PATH
default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01
default "src/vendorcode/amd/pi/00670F00" if AMD_APU_MERLINFALCON
default "src/vendorcode/amd/pi/00670F00" if AMD_APU_STONEYRIDGE || AMD_APU_PRAIRIEFALCON
- default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01
help
Specify where to find the AGESA header files
for AMD platform initialization.
@@ -46,7 +45,6 @@ config AGESA_BINARY_PI_FILE
default "3rdparty/amd_blobs/stoneyridge/pi/CZ/\$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_MERLINFALCON && USE_AMD_BLOBS
default "3rdparty/amd_blobs/stoneyridge/pi/ST/\$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_PRAIRIEFALCON && USE_AMD_BLOBS
default "3rdparty/amd_blobs/stoneyridge/pi/ST/\$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_STONEYRIDGE && USE_AMD_BLOBS
- default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01
help
Specify the binary file to use for AMD platform initialization.
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index 8f27d64f20..25e3652751 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -30,7 +30,7 @@
subdirs-y += 00670F00
-ifeq ($(CONFIG_CPU_AMD_PI_00630F01)$(CONFIG_CPU_AMD_PI_00730F01)$(CONFIG_CPU_AMD_PI_00660F01),y)
+ifeq ($(CONFIG_CPU_AMD_PI_00630F01)$(CONFIG_CPU_AMD_PI_00730F01),y)
# AGESA V5 Files
AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH))
@@ -52,10 +52,6 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch
AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common
-ifeq ($(CONFIG_CPU_AMD_PI_00660F01),y)
-AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Kern
-AGESA_INC += -I$(AGESA_ROOT)/Proc/Psp/PspBaseLib
-endif
ifeq ($(CONFIG_CPU_AMD_PI_00630F01),y)
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS
endif
@@ -111,11 +107,6 @@ endef
agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/*.[cS])
-ifeq ($(CONFIG_CPU_AMD_PI_00660F01),y)
-agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Kern/KernImc/*.[cS])
-agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS])
-agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS])
-endif
ifeq ($(CONFIG_HUDSON_IMC_FWM),y)
agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/imc/*.c)
endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 16:45:23 +0000