diff options
| -rw-r--r-- | src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 10 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 12 | ||||
| -rw-r--r-- | src/mainboard/google/snow/romstage.c | 7 |
3 files changed, 17 insertions, 12 deletions
diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c index e3d46ab2d5..f2c228d339 100644 --- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c @@ -158,8 +158,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, /* Send PALL command */ dmc_config_prech(mem, dmc); - /* Send NOP, MRS and ZQINIT commands */ - dmc_config_mrs(mem, dmc); + if (mem_reset) { + /* Send NOP, MRS and ZQINIT commands. + * Sending MRS command will reset the DRAM. We should not be + * reseting the DRAM after resume, this will lead to memory + * corruption as DRAM content is lost after DRAM reset + */ + dmc_config_mrs(mem, dmc); + } if (mem->gate_leveling_enable) { val = PHY_CON0_RESET_VAL; diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c index 74ee7e93a1..ebfe1e1a0f 100644 --- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c @@ -184,9 +184,15 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) writel(mem->timing_power, &drex0->timingpower); writel(mem->timing_power, &drex1->timingpower); - /* Send NOP, MRS and ZQINIT commands */ - dmc_config_mrs(mem, drex0); - dmc_config_mrs(mem, drex1); + /* Send NOP, MRS and ZQINIT commands. + * Sending MRS command will reset the DRAM. We should not be + * reseting the DRAM after resume, this will lead to memory + * corruption as DRAM content is lost after DRAM reset. + */ + if (reset) { + dmc_config_mrs(mem, drex0); + dmc_config_mrs(mem, drex1); + } if (mem->gate_leveling_enable) { diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index f69fb1f7eb..92fa21e4a1 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -141,13 +141,6 @@ static void setup_memory(struct mem_timings *mem, int is_resume) mem->mpll_mdiv, mem->frequency_mhz); - /* FIXME Currently memory initialization with mem_reset on normal boot - * will cause resume to fail (even if we don't do mem_reset on resume), - * and the workaround is to temporarily always enable "is_resume". - * This should be removed when the root cause of resume issue is found. - */ - is_resume = 1; - if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { die("Failed to initialize memory controller.\n"); } |