diff options
| -rw-r--r-- | src/northbridge/intel/i5000/udelay.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c index e462bbcdf4..ce4c7b360e 100644 --- a/src/northbridge/intel/i5000/udelay.c +++ b/src/northbridge/intel/i5000/udelay.c @@ -22,7 +22,7 @@ #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> -#include <console/console.h> + /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock */ |