diff options
20 files changed, 596 insertions, 0 deletions
diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig new file mode 100644 index 0000000000..1c39839154 --- /dev/null +++ b/src/mainboard/acer/Kconfig @@ -0,0 +1,18 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_ACER + +choice + prompt "Mainboard model" + +source "src/mainboard/acer/*/Kconfig.name" + +endchoice + +source "src/mainboard/acer/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Acer" + +endif # VENDOR_ACER diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name new file mode 100644 index 0000000000..bb177f9e49 --- /dev/null +++ b/src/mainboard/acer/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ACER + bool "Acer" diff --git a/src/mainboard/acer/g43t-am3/Kconfig b/src/mainboard/acer/g43t-am3/Kconfig new file mode 100644 index 0000000000..941070ed2d --- /dev/null +++ b/src/mainboard/acer/g43t-am3/Kconfig @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ACER_G43T_AM3 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801JX + select SUPERIO_ITE_IT8720F + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_2048 + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select DRIVERS_I2C_CK505 + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + +config VGA_BIOS_ID + string + default "8086,2e22" + +config MAINBOARD_DIR + string + default "acer/g43t-am3" + +config MAINBOARD_PART_NUMBER + string + default "G43T-AM3" + +endif # BOARD_ACER_G43T_AM3 diff --git a/src/mainboard/acer/g43t-am3/Kconfig.name b/src/mainboard/acer/g43t-am3/Kconfig.name new file mode 100644 index 0000000000..a9b34ff25f --- /dev/null +++ b/src/mainboard/acer/g43t-am3/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ACER_G43T_AM3 + bool "G43T-AM3" diff --git a/src/mainboard/acer/g43t-am3/Makefile.inc b/src/mainboard/acer/g43t-am3/Makefile.inc new file mode 100644 index 0000000000..ede8d87e92 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += cstates.c +romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/acer/g43t-am3/acpi/ec.asl b/src/mainboard/acer/g43t-am3/acpi/ec.asl new file mode 100644 index 0000000000..2997587d82 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/acer/g43t-am3/acpi/ich10_pci_irqs.asl b/src/mainboard/acer/g43t-am3/acpi/ich10_pci_irqs.asl new file mode 100644 index 0000000000..b7588dcc41 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/acpi/ich10_pci_irqs.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 + */ + +If (PICM) { + Return (Package() { + /* PCI slot */ + Package() { 0x0001ffff, 0, 0, 0x14}, + Package() { 0x0001ffff, 1, 0, 0x15}, + Package() { 0x0001ffff, 2, 0, 0x16}, + Package() { 0x0001ffff, 3, 0, 0x17}, + + Package() { 0x0002ffff, 0, 0, 0x15}, + Package() { 0x0002ffff, 1, 0, 0x16}, + Package() { 0x0002ffff, 2, 0, 0x17}, + Package() { 0x0002ffff, 3, 0, 0x14}, + }) +} Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} diff --git a/src/mainboard/acer/g43t-am3/acpi/superio.asl b/src/mainboard/acer/g43t-am3/acpi/superio.asl new file mode 100644 index 0000000000..9f3900b86c --- /dev/null +++ b/src/mainboard/acer/g43t-am3/acpi/superio.asl @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8720F_SHOW_SP1 +#undef IT8720F_SHOW_SP2 +#undef IT8720F_SHOW_EC +#undef IT8720F_SHOW_KBCK +#undef IT8720F_SHOW_KBCM +#undef IT8720F_SHOW_GPIO +#undef IT8720F_SHOW_CIR +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8720F_SHOW_EC 1 +#define IT8720F_SHOW_KBCK 1 +#define IT8720F_SHOW_KBCM 1 +#define IT8720F_SHOW_GPIO 1 +#include <superio/ite/it8720f/acpi/superio.asl> diff --git a/src/mainboard/acer/g43t-am3/acpi_tables.c b/src/mainboard/acer/g43t-am3/acpi_tables.c new file mode 100644 index 0000000000..1485b67439 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/i82801jx/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ +} diff --git a/src/mainboard/acer/g43t-am3/board_info.txt b/src/mainboard/acer/g43t-am3/board_info.txt new file mode 100644 index 0000000000..aaf657b583 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default new file mode 100644 index 0000000000..706f5dd551 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=64M diff --git a/src/mainboard/acer/g43t-am3/cmos.layout b/src/mainboard/acer/g43t-am3/cmos.layout new file mode 100644 index 0000000000..5f51bb8398 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/cmos.layout @@ -0,0 +1,73 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi + +# coreboot config options: cpu + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size + + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/acer/g43t-am3/cstates.c b/src/mainboard/acer/g43t-am3/cstates.c new file mode 100644 index 0000000000..21b18b9e8d --- /dev/null +++ b/src/mainboard/acer/g43t-am3/cstates.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/acer/g43t-am3/data.vbt b/src/mainboard/acer/g43t-am3/data.vbt Binary files differnew file mode 100644 index 0000000000..646adbae1b --- /dev/null +++ b/src/mainboard/acer/g43t-am3/data.vbt diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb new file mode 100644 index 0000000000..4266861bdc --- /dev/null +++ b/src/mainboard/acer/g43t-am3/devicetree.cb @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xacac off end + end + end + device domain 0 on # PCI domain + subsystemid 0x8086 0x0028 inherit + device pci 0.0 on end # Host Bridge + device pci 2.0 on end # Integrated graphics controller + device pci 2.1 on end # Integrated graphics controller 2 + device pci 3.0 off end # ME + device pci 3.1 off end # ME + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x40" + + # Set AHCI mode. + register "sata_port_map" = "0x3f" + register "sata_clock_request" = "0" + + # Enable PCIe ports 0,1 as slots. + register "pcie_slot_implemented" = "0x3" + + # "Additional LPC IO decode ranges": used for SuperIO's + # Environment Controller on 0xa15/0xa16 + register "gen1_dec" = "0x00fc0a01" + + device pci 19.0 on end # GBE + device pci 1a.0 on end # USB + device pci 1a.1 on end # USB + device pci 1a.2 on end # USB + device pci 1a.7 on end # USB + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on end # PCIe 2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8720f # Super I/O + register "ec.smbus_en" = "1" + register "ec.smbus_24mhz" = "1" + register "TMPIN1.mode" = "THERMAL_DIODE" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_PECI" + register "TMPIN3.offset" = "100" + register "TMPIN3.min" = "0" + register "TMPIN3.max" = "100" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" # CPU fan + register "FAN1.smart.tmpin" = "3" + register "FAN1.smart.tmp_off" = "0" + register "FAN1.smart.tmp_start" = "50" + register "FAN1.smart.tmp_full" = "90" + register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.full_lmt" = "1" + register "FAN1.smart.smoothing" = "0" + register "FAN1.smart.pwm_start" = "30" + register "FAN1.smart.slope" = "0x0d" + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" # System fan + register "FAN2.smart.tmpin" = "2" + register "FAN2.smart.tmp_off" = "0" + register "FAN2.smart.tmp_start" = "40" + register "FAN2.smart.tmp_full" = "90" + register "FAN2.smart.tmp_delta" = "2" + register "FAN2.smart.full_lmt" = "0" + register "FAN2.smart.smoothing" = "0" + register "FAN2.smart.pwm_start" = "48" + register "FAN2.smart.slope" = "0x20" + register "FAN3.mode" = "FAN_MODE_OFF" # Not connected + + register "ec.vin_mask" = "VIN_ALL" + + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # COM 1 + device pnp 2e.2 off end # COM 2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment controller + io 0x60 = 0xa10 + io 0x62 = 0xa00 + irq 0x70 = 0x00 + irq 0xf0 = 0x00 + irq 0xf1 = 0x00 + irq 0xf2 = 0x00 + irq 0xf3 = 0x00 + irq 0xf4 = 0x60 + irq 0xf5 = 0x00 + irq 0xf6 = 0x00 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x060 + irq 0x70 = 0x1 + io 0x62 = 0x064 + irq 0xf0 = 0x00 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 0x0c + irq 0xf0 = 0x00 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x000 + io 0x62 = 0xa20 + io 0x64 = 0xa30 + irq 0xc0 = 0x01 # Simple IO Set 1 + irq 0xc1 = 0x0c # Simple IO Set 2 + irq 0xc2 = 0x70 # Simple IO Set 3 + irq 0xc3 = 0x00 # Simple IO Set 4 + irq 0xc8 = 0x01 # Simple IO Set 1 Output + irq 0xc9 = 0x0c # Simple IO Set 2 Output + irq 0xca = 0x00 # Simple IO Set 3 Output + irq 0xcb = 0x00 # Simple IO Set 4 Output + irq 0xf0 = 0x00 + irq 0xf1 = 0x00 + irq 0xf2 = 0x00 + irq 0xf3 = 0x00 + irq 0xf4 = 0x00 + irq 0xf5 = 0x00 + irq 0xf6 = 0x00 + irq 0xf7 = 0x00 + irq 0xf8 = 0x12 + irq 0xf9 = 0x02 + irq 0xfa = 0x13 + irq 0xfb = 0x02 + #irq 0xfc = 0xef # VID Input + irq 0xfd = 0x00 + irq 0xfe = 0x00 + end + device pnp 2e.a off end # CIR + end + end + device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5) + device pci 1f.3 on # SMBus + chip drivers/i2c/ck505 # IDT CV194 + register "mask" = "{ 0xff, 0xff, 0xff, 0x00, + 0xff, 0x00, 0x00, 0x00, + 0x00, 0xff, 0xff, 0xff, + 0x00, 0xff }" + register "regs" = "{ 0x57, 0xd9, 0xfe, 0xff, + 0xff, 0x00, 0x00, 0x00, + 0x00, 0x24, 0x7d, 0x96, + 0x00, 0x9d }" + device i2c 69 on end + end + end + device pci 1f.4 off end + device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode) + device pci 1f.6 off end # Thermal Subsystem + end + end +end diff --git a/src/mainboard/acer/g43t-am3/dsdt.asl b/src/mainboard/acer/g43t-am3/dsdt.asl new file mode 100644 index 0000000000..cf2395cf9a --- /dev/null +++ b/src/mainboard/acer/g43t-am3/dsdt.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20090811 // OEM revision +) +{ + // global NVS and variables + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/i82801jx/acpi/globalnvs.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801jx/acpi/ich10.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/acer/g43t-am3/early_init.c b/src/mainboard/acer/g43t-am3/early_init.c new file mode 100644 index 0000000000..b34ab4651b --- /dev/null +++ b/src/mainboard/acer/g43t-am3/early_init.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <southbridge/intel/i82801jx/i82801jx.h> +#include <northbridge/intel/x4x/x4x.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8720f/it8720f.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) + +void bootblock_mainboard_early_init(void) +{ + /* Set up GPIOs on Super I/O. */ + ite_reg_write(GPIO_DEV, 0x25, 0x00); // GPIO set 1 + ite_reg_write(GPIO_DEV, 0x26, 0x0c); // GPIO set 2 + ite_reg_write(GPIO_DEV, 0x27, 0x70); // GPIO set 3 + ite_reg_write(GPIO_DEV, 0x28, 0x40); // GPIO set 4 + ite_reg_write(GPIO_DEV, 0x29, 0x00); // GPIO set 5 + + /* Enable 3VSB during Suspend-to-RAM */ + ite_enable_3vsbsw(GPIO_DEV); + + /* Delay PWROK2 after 3VSBSW# during resume from Suspend-to-RAM */ + ite_delay_pwrgd3(GPIO_DEV); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; +} diff --git a/src/mainboard/acer/g43t-am3/gma-mainboard.ads b/src/mainboard/acer/g43t-am3/gma-mainboard.ads new file mode 100644 index 0000000000..c9e4326924 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/acer/g43t-am3/gpio.c b/src/mainboard/acer/g43t-am3/gpio.c new file mode 100644 index 0000000000..38239baf79 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/gpio.c @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio9 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio18 = GPIO_BLINK, + +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + +}; diff --git a/src/mainboard/acer/g43t-am3/hda_verb.c b/src/mainboard/acer/g43t-am3/hda_verb.c new file mode 100644 index 0000000000..32a9b25874 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/hda_verb.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0888, + 0x1025024c, // Subsystem ID + 14, // Number of entries + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x11, 0x014b7140), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19851), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1c, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, 0x18567130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + /* HDMI */ + 0x80862803, + 0x80860101, + 1, + + AZALIA_PIN_CFG(0, 0x03, 0x18560010) +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); |