diff options
| -rw-r--r-- | src/mainboard/biostar/a68n_5200/Kconfig | 5 | ||||
| -rw-r--r-- | src/mainboard/biostar/a68n_5200/devicetree.cb | 48 | ||||
| -rw-r--r-- | src/mainboard/biostar/a68n_5200/romstage.c | 67 |
3 files changed, 96 insertions, 24 deletions
diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig index 55dfb11d73..183f0f5fec 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ b/src/mainboard/biostar/a68n_5200/Kconfig @@ -2,6 +2,8 @@ # This file is part of the coreboot project. # # Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2016 Edward O'Callaghan <funfunctor@folklore1984.net> +# Copyright (C) 2017 Damien Zammit <damien@zamaudio.com> # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -20,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select SUPERIO_ITE_IT8728F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE @@ -57,6 +60,6 @@ config ONBOARD_VGA_IS_PRIMARY config HUDSON_LEGACY_FREE bool - default y + default n endif # BOARD_BIOSTAR_A68N5200 diff --git a/src/mainboard/biostar/a68n_5200/devicetree.cb b/src/mainboard/biostar/a68n_5200/devicetree.cb index a027db9815..d102ed1603 100644 --- a/src/mainboard/biostar/a68n_5200/devicetree.cb +++ b/src/mainboard/biostar/a68n_5200/devicetree.cb @@ -2,6 +2,8 @@ # This file is part of the coreboot project. # # Copyright (C) 2013 Advanced Micro Devices, Inc. +# Copyright (C) 2016 Edward O'Callaghan <funfunctor@folklore1984.net> +# Copyright (C) 2017 Damien Zammit <damien@zamaudio.com> # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -29,10 +31,10 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector + device pci 2.2 off end # mPCIe slot + device pci 2.3 off end # Realtek NIC + device pci 2.4 off end # Edge Connector + device pci 2.5 off end # Edge Connector end #chip northbridge/amd/agesa/family16kb chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus @@ -51,8 +53,42 @@ chip northbridge/amd/agesa/family16kb/root_complex end end # SM device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + #register "multi_function_register_1" = "0x01" + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 4 + end + device pnp 2e.4 on # Hardware Monitor + io 0x60 = 0xa00 + io 0x62 = 0xa20 + irq 0x70 = 0 + irq 0xf1 = 0x00 + irq 0xf2 = 0x04 + irq 0xf3 = 0xa0 + irq 0xf5 = 0x0f + irq 0xf9 = 0xa0 + irq 0xfa = 0x04 + end + device pnp 2e.5 on # KBC + io 0x60 = 0x60 + end + device pnp 2e.6 off end # KBC? + device pnp 2e.7 off end # GPIO + device pnp 2e.8 off end + device pnp 2e.9 off end + device pnp 2e.a off end # IR + end # ITE IT8728F + end #LPC + device pci 14.7 off end # SD end #chip southbridge/amd/agesa/hudson device pci 18.0 on end diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c index 8190cb7711..8df2d95a48 100644 --- a/src/mainboard/biostar/a68n_5200/romstage.c +++ b/src/mainboard/biostar/a68n_5200/romstage.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Edward O'Callaghan <funfunctor@folklore1984.net> + * Copyright (C) 2017 Damien Zammit <damien@zamaudio.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,31 +26,62 @@ #include <commonlib/loglevel.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SB_MMIO 0xFED80000 +#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) + +#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) +#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO) + +static void sbxxx_enable_48mhzout(void) +{ + /* most likely programming to 48MHz out signal */ + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ + u32 reg32; + reg32 = SB_MMIO_MISC32(0x28); + reg32 &= 0xfff8ffff; + SB_MMIO_MISC32(0x28) = reg32; + + /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ + reg32 = SB_MMIO_MISC32(0x40); + reg32 &= 0xffffbffb; + SB_MMIO_MISC32(0x40) = reg32; +} void board_BeforeAgesa(struct sysinfo *cb) { - int i; - u32 val; - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xea, 0xcd6); + u8 byte; + + /* Enable the AcpiMmio space */ + outb(0x24, 0xcd6); outb(0x1, 0xcd7); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); + if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + + if (IS_ENABLED(CONFIG_POST_DEVICE_LPC)) + hudson_lpc_port80(); + + /* enable SIO LPC decode */ + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - for (i = 0; i < 200000; i++) - val = inb(0xcd6); + /* run ite */ + sbxxx_enable_48mhzout(); + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } |