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-rw-r--r--src/southbridge/amd/agesa/hudson/hudson.h5
-rw-r--r--src/southbridge/amd/agesa/hudson/lpc.c11
-rw-r--r--src/southbridge/amd/cimx/sb700/lpc.c13
-rw-r--r--src/southbridge/amd/cimx/sb700/lpc.h4
-rw-r--r--src/southbridge/amd/cimx/sb800/lpc.c10
-rw-r--r--src/southbridge/amd/cimx/sb800/lpc.h5
-rw-r--r--src/southbridge/amd/cimx/sb900/lpc.c13
-rw-r--r--src/southbridge/amd/cimx/sb900/lpc.h5
8 files changed, 41 insertions, 25 deletions
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h
index 6f757eb72e..50f1738b4e 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.h
+++ b/src/southbridge/amd/agesa/hudson/hudson.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -50,7 +51,9 @@
#define REV_HUDSON_A11 0x11
#define REV_HUDSON_A12 0x12
-#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
+#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
+#define SPI_ROM_ENABLE 0x02
+#define SPI_BASE_ADDRESS 0xFEC10000
#ifndef __SMM__
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index 71aaf6fe91..c8051ec42d 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -87,8 +87,6 @@ static void hudson_lpc_read_resources(device_t dev)
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
- pci_get_resource(dev, 0xA0); /* SPI ROM base address */
-
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0;
@@ -102,6 +100,9 @@ static void hudson_lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ /* Add a memory resource for the SPI BAR. */
+ fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
+
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
@@ -115,12 +116,10 @@ static void hudson_lpc_set_resources(struct device *dev)
struct resource *res;
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
- res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER);
- res->base |= PCI_COMMAND_MEMORY;
+ res = find_resource(dev, 2);
+ pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
pci_dev_set_resources(dev);
-
-
}
/**
diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c
index 91d7d2fd51..5d05762f55 100644
--- a/src/southbridge/amd/cimx/sb700/lpc.c
+++ b/src/southbridge/amd/cimx/sb700/lpc.c
@@ -46,8 +46,6 @@ void lpc_read_resources(device_t dev)
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
- pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */
-
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0;
@@ -61,6 +59,9 @@ void lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ /* Add a memory resource for the SPI BAR. */
+ fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
+
res = new_resource(dev, 3);
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
@@ -75,11 +76,13 @@ void lpc_set_resources(struct device *dev)
struct resource *res;
printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__);
+
+ /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
+ res = find_resource(dev, 2);
+ pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
+
pci_dev_set_resources(dev);
- /* Specical case. SPI Base Address. The SpiRomEnable should be set. */
- res = find_resource(dev, SPIROM_BASE_ADDRESS);
- pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__);
}
diff --git a/src/southbridge/amd/cimx/sb700/lpc.h b/src/southbridge/amd/cimx/sb700/lpc.h
index e110026126..b30f2470d4 100644
--- a/src/southbridge/amd/cimx/sb700/lpc.h
+++ b/src/southbridge/amd/cimx/sb700/lpc.h
@@ -21,7 +21,9 @@
#define _SB700_LPC_H_
-#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */
+#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
+#define SPI_ROM_ENABLE 0x02
+#define SPI_BASE_ADDRESS 0xFEC10000
void lpc_read_resources(device_t dev);
void lpc_set_resources(device_t dev);
diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c
index a1e0dc96df..519e3c1175 100644
--- a/src/southbridge/amd/cimx/sb800/lpc.c
+++ b/src/southbridge/amd/cimx/sb800/lpc.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -33,8 +34,6 @@ void lpc_read_resources(device_t dev)
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
- pci_get_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); /* SPI ROM base address */
-
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0;
@@ -48,6 +47,9 @@ void lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ /* Add a memory resource for the SPI BAR. */
+ fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
+
res = new_resource(dev, 3);
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
@@ -64,8 +66,8 @@ void lpc_set_resources(struct device *dev)
printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n");
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
- res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER);
- res->base |= PCI_COMMAND_MEMORY;
+ res = find_resource(dev, 2);
+ pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
pci_dev_set_resources(dev);
diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h
index 575b9f7a75..8a657d8559 100644
--- a/src/southbridge/amd/cimx/sb800/lpc.h
+++ b/src/southbridge/amd/cimx/sb800/lpc.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,7 +21,9 @@
#ifndef _SB800_LPC_H_
#define _SB800_LPC_H_
-#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 /* SPI ROM base address */
+#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
+#define SPI_ROM_ENABLE 0x02
+#define SPI_BASE_ADDRESS 0xFEC10000
void lpc_read_resources(device_t dev);
void lpc_set_resources(device_t dev);
diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c
index 5b414f41a5..ce1be11da7 100644
--- a/src/southbridge/amd/cimx/sb900/lpc.c
+++ b/src/southbridge/amd/cimx/sb900/lpc.c
@@ -31,8 +31,6 @@ void lpc_read_resources(device_t dev)
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
- pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */
-
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0;
@@ -46,6 +44,9 @@ void lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ /* Add a memory resource for the SPI BAR. */
+ fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
+
res = new_resource(dev, 3);
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
@@ -60,11 +61,13 @@ void lpc_set_resources(struct device *dev)
struct resource *res;
printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - Start.\n");
+
+ /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
+ res = find_resource(dev, 2);
+ pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
+
pci_dev_set_resources(dev);
- /* Specical case. SPI Base Address. The SpiRomEnable should be set. */
- res = find_resource(dev, SPIROM_BASE_ADDRESS);
- pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - End.\n");
}
diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h
index c0c5f20195..66f3ccd8cd 100644
--- a/src/southbridge/amd/cimx/sb900/lpc.h
+++ b/src/southbridge/amd/cimx/sb900/lpc.h
@@ -20,8 +20,9 @@
#ifndef _SB900_LPC_H_
#define _SB900_LPC_H_
-
-#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */
+#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
+#define SPI_ROM_ENABLE 0x02
+#define SPI_BASE_ADDRESS 0xFEC10000
void lpc_read_resources(device_t dev);
void lpc_set_resources(device_t dev);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 19:18:48 +0000