diff options
| -rw-r--r-- | src/arch/x86/include/arch/cpu.h | 7 | ||||
| -rw-r--r-- | src/arch/x86/postcar.c | 12 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/temp_ram_exit.c | 5 |
3 files changed, 20 insertions, 4 deletions
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 8a44ef96c0..4327abed55 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -297,6 +297,13 @@ void *postcar_commit_mtrrs(struct postcar_frame *pcf); * utilizes prog_run() internally. */ void run_postcar_phase(struct postcar_frame *pcf); + +/* + * Systems without a native coreboot cache-as-ram teardown may implement + * this to use an alternate method. + */ +void late_car_teardown(void); + #endif #endif /* ARCH_CPU_H */ diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index 34a4335121..7b5be6e9f0 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -13,18 +13,22 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> #include <cbmem.h> #include <console/console.h> #include <main_decl.h> #include <program_loading.h> #include <soc/intel/common/util.h> -#include <fsp/util.h> + +/* + * Systems without a native coreboot cache-as-ram teardown may implement + * this to use an alternate method. + */ +__attribute__((weak)) void late_car_teardown(void) { /* do nothing */ } void main(void) { - /* Call TempRamExit FSP API if enabled. */ - if (IS_ENABLED(CONFIG_FSP_CAR)) - fsp_temp_ram_exit(); + late_car_teardown(); console_init(); diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 21eb367e8c..6b3a999f16 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -47,3 +47,8 @@ void fsp_temp_ram_exit(void) die("TempRamExit returned an error!\n"); } } + +void late_car_teardown(void) +{ + fsp_temp_ram_exit(); +} |