diff options
| -rw-r--r-- | src/southbridge/amd/sb800/sata.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c index db4d20f54c..debd448501 100644 --- a/src/southbridge/amd/sb800/sata.c +++ b/src/southbridge/amd/sb800/sata.c @@ -53,6 +53,15 @@ static int sata_drive_detect(int portnum, u16 iobar) return 0; } +static const u32 sata_phy[][3] = { + {0x0056A607, 0x00061400, 0x00061302}, /* port 0 */ + {0x0056A607, 0x00061400, 0x00061302}, /* port 1 */ + {0x0056A607, 0x00061402, 0x00064300}, /* port 2 */ + {0x0056A607, 0x00061402, 0x00064300}, /* port 3 */ + {0x0056A700, 0x00061502, 0x00064302}, /* port 4 */ + {0x0056A700, 0x00061502, 0x00064302} /* port 5 */ +}; + static void sata_init(struct device *dev) { u8 byte; @@ -139,14 +148,14 @@ static void sata_init(struct device *dev) pci_write_config8(dev, 0x46, 0x20); /* RPR8.4 */ - /* Port 0 */ + /* Port 0 - 5 */ for (i = 0; i < 6; i++) { pci_write_config16(dev, 0x84, 0x3006 | i << 9); - pci_write_config32(dev, 0x94, 0x0056A700); + pci_write_config32(dev, 0x94, sata_phy[i][0]); /* Gen 3 */ pci_write_config16(dev, 0x84, 0x2006 | i << 9); - pci_write_config32(dev, 0x94, 0x00061400); + pci_write_config32(dev, 0x94, sata_phy[i][1]); /* Gen 2 */ pci_write_config16(dev, 0x84, 0x1006 | i << 9); - pci_write_config32(dev, 0x94, 0x00061302); + pci_write_config32(dev, 0x94, sata_phy[i][2]); /* Gen 1 */ } /* Enable the I/O, MM, BusMaster access for SATA */ |