diff options
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/data_fabric.h | 15 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/data_fabric.h | 15 |
2 files changed, 17 insertions, 13 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index 7888a9c31a..2c0396aeb3 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -10,6 +10,21 @@ #define BROADCAST_FABRIC_ID 0xff +/* D18F0 - Fabric Configuration registers */ +#define D18F0_MMIO_BASE0 0x200 +#define D18F0_MMIO_LIMIT0 0x204 +#define D18F0_MMIO_SHIFT 16 +#define D18F0_MMIO_CTRL0 0x208 +#define MMIO_NP BIT(12) +#define MMIO_DST_FABRIC_ID_SHIFT 4 +#define MMIO_WE BIT(1) +#define MMIO_RE BIT(0) + +/* The number of data fabric MMIO registers is SoC-specific */ +#define NB_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0) +#define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0) +#define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0) + uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id); void data_fabric_write32(uint8_t function, uint16_t reg, uint8_t instance_id, uint32_t data); diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 3a19318cfd..3a1f2c714a 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -8,22 +8,11 @@ /* D18F0 - Fabric Configuration registers */ #define IOMS0_FABRIC_ID 9 +#define NUM_NB_MMIO_REGS 8 + #define D18F0_VGAEN 0x80 #define VGA_ADDR_ENABLE BIT(0) -#define D18F0_MMIO_BASE0 0x200 -#define D18F0_MMIO_LIMIT0 0x204 -#define D18F0_MMIO_SHIFT 16 -#define D18F0_MMIO_CTRL0 0x208 -#define MMIO_NP BIT(12) -#define MMIO_DST_FABRIC_ID_SHIFT 4 -#define MMIO_WE BIT(1) -#define MMIO_RE BIT(0) -#define NUM_NB_MMIO_REGS 8 -#define NB_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0) -#define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0) -#define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0) - #define D18F0_DRAM_HOLE_CTL 0x104 #define DRAM_HOLE_CTL_VALID BIT(0) #define DRAM_HOLE_CTL_BASE_SHFT 24 |