diff options
| -rw-r--r-- | src/northbridge/intel/common/Kconfig | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/common/Makefile.inc | 17 | ||||
| -rw-r--r-- | src/northbridge/intel/common/mrc_cache.c (renamed from src/northbridge/intel/sandybridge/mrccache.c) | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/common/mrc_cache.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/Kconfig | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/mrccache.c | 247 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/Kconfig | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/nehalem.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/Kconfig | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 2 |
14 files changed, 28 insertions, 264 deletions
diff --git a/src/northbridge/intel/common/Kconfig b/src/northbridge/intel/common/Kconfig new file mode 100644 index 0000000000..80593d6bf8 --- /dev/null +++ b/src/northbridge/intel/common/Kconfig @@ -0,0 +1,2 @@ +config NORTHBRIDGE_INTEL_COMMON_MRC_CACHE + def_bool n diff --git a/src/northbridge/intel/common/Makefile.inc b/src/northbridge/intel/common/Makefile.inc new file mode 100644 index 0000000000..73427cbbb1 --- /dev/null +++ b/src/northbridge/intel/common/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Alexander Couzens <lynxis@fe80.eu> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-$(CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE) += mrc_cache.c +ramstage-$(CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE) += mrc_cache.c diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/common/mrc_cache.c index f243c27464..82b1005a7a 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/common/mrc_cache.c @@ -22,11 +22,9 @@ #include <ip_checksum.h> #include <device/device.h> #include <cbmem.h> -#include "pei_data.h" -#include "sandybridge.h" -#include <northbridge/intel/common/mrc_cache.h> #include <spi-generic.h> #include <spi_flash.h> +#include "mrc_cache.h" /* convert a pointer to flash area into the offset inside the flash */ static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { @@ -62,6 +60,7 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { size_t region_size = 0; + *mrc_region_ptr = NULL; if (IS_ENABLED(CONFIG_CHROMEOS)) { struct region_device rdev; @@ -69,8 +68,7 @@ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { region_size = region_device_sz(&rdev); *mrc_region_ptr = rdev_mmap_full(&rdev); - } else - *mrc_region_ptr = NULL; + } } else { *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", CBFS_TYPE_MRC_CACHE, diff --git a/src/northbridge/intel/common/mrc_cache.h b/src/northbridge/intel/common/mrc_cache.h index 5c66ccc34a..408a420a1a 100644 --- a/src/northbridge/intel/common/mrc_cache.h +++ b/src/northbridge/intel/common/mrc_cache.h @@ -12,4 +12,6 @@ struct mrc_data_container { u8 mrc_data[0]; // Variable size, platform/run time dependent. } __attribute__ ((packed)); +struct mrc_data_container *find_current_mrc_cache(void); + #endif /* NORTHBRIDGE_INTEL_COMMON_MRC_CACHE_H */ diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 69550ffcfd..5e592337f2 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -18,6 +18,7 @@ config NORTHBRIDGE_INTEL_HASWELL select CPU_INTEL_HASWELL select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select INTEL_DDI select INTEL_DP select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 1dd7f76712..f198b7c027 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -20,12 +20,10 @@ ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c -ramstage-y += mrccache.c ramstage-y += minihd.c romstage-y += ram_calc.c romstage-y += raminit.c -romstage-y += mrccache.c romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/walkcbfs.S diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index c560428a06..6e587f8640 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -213,8 +213,6 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ -struct mrc_data_container; -struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c deleted file mode 100644 index 09bf73fcc7..0000000000 --- a/src/northbridge/intel/haswell/mrccache.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <bootstate.h> -#include <console/console.h> -#include <cbfs.h> -#include <fmap.h> -#include <ip_checksum.h> -#include <northbridge/intel/common/mrc_cache.h> -#include <device/device.h> -#include <cbmem.h> -#include "pei_data.h" -#include "haswell.h" -#include <spi-generic.h> -#include <spi_flash.h> - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - -static struct mrc_data_container *next_mrc_block( - struct mrc_data_container *mrc_cache) -{ - /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; - if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { - mrc_size &= ~(MRC_DATA_ALIGN - 1UL); - mrc_size += MRC_DATA_ALIGN; - } - - u8 *region_ptr = (u8*)mrc_cache; - region_ptr += mrc_size; - return (struct mrc_data_container *)region_ptr; -} - -static int is_mrc_cache(struct mrc_data_container *mrc_cache) -{ - return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); -} - -/* Right now, the offsets for the MRC cache area are hard-coded in the - * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make - * this more flexible, there are two of options: - * - Have each mainboard Kconfig supply a hard-coded offset - * - Use CBFS - */ -static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) -{ - size_t region_size = 0; - *mrc_region_ptr = NULL; - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - region_size = region_device_sz(&rdev); - *mrc_region_ptr = rdev_mmap_full(&rdev); - } - } else { - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - ®ion_size); - } - return region_size; -} - -/* - * Find the largest index block in the MRC cache. Return NULL if non is - * found. - */ -static struct mrc_data_container *find_current_mrc_cache_local - (struct mrc_data_container *mrc_cache, u32 region_size) -{ - u32 region_end; - u32 entry_id = 0; - struct mrc_data_container *mrc_next = mrc_cache; - - region_end = (u32) mrc_cache + region_size; - - /* Search for the last filled entry in the region */ - while (is_mrc_cache(mrc_next)) { - entry_id++; - mrc_cache = mrc_next; - mrc_next = next_mrc_block(mrc_next); - if ((u32)mrc_next >= region_end) { - /* Stay in the MRC data region */ - break; - } - } - - if (entry_id == 0) { - printk(BIOS_ERR, "%s: No valid MRC cache found.\n", __func__); - return NULL; - } - - /* Verify checksum */ - if (mrc_cache->mrc_checksum != - compute_ip_checksum(mrc_cache->mrc_data, - mrc_cache->mrc_data_size)) { - printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); - return NULL; - } - - printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, - entry_id - 1); - - return mrc_cache; -} - -/* SPI code needs malloc/free. - * Also unknown if writing flash from XIP-flash code is a good idea - */ - -/* find the first empty block in the MRC cache area. - * If there's none, return NULL. - * - * @mrc_cache_base - base address of the MRC cache area - * @mrc_cache - current entry (for which we need to find next) - * @region_size - total size of the MRC cache area - */ -static struct mrc_data_container *find_next_mrc_cache - (struct mrc_data_container *mrc_cache_base, - struct mrc_data_container *mrc_cache, - u32 region_size) -{ - u32 region_end = (u32) mrc_cache_base + region_size; - - mrc_cache = next_mrc_block(mrc_cache); - if ((u32)mrc_cache >= region_end) { - /* Crossed the boundary */ - mrc_cache = NULL; - printk(BIOS_DEBUG, "%s: no available entries found\n", - __func__); - } else { - printk(BIOS_DEBUG, - "%s: picked next entry from cache block at %p\n", - __func__, mrc_cache); - } - - return mrc_cache; -} - -static void update_mrc_cache(void *unused) -{ - printk(BIOS_DEBUG, "Updating MRC cache data.\n"); - struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); - struct mrc_data_container *cache, *cache_base; - u32 cache_size; - - if (!current) { - printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); - return; - } - if (current->mrc_data_size == -1) { - printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); - return; - } - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - cache = find_current_mrc_cache_local(cache_base, cache_size); - - if (cache && (cache->mrc_data_size == current->mrc_data_size) && - (memcmp(cache, current, cache->mrc_data_size) == 0)) { - printk(BIOS_DEBUG, - "MRC data in flash is up to date. No update.\n"); - return; - } - - // 1. use spi_flash_probe() to find the flash, then - spi_init(); - struct spi_flash *flash = spi_flash_probe(0, 0); - if (!flash) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return; - } - - // 2. look up the first unused block - if (cache) - cache = find_next_mrc_cache(cache_base, cache, cache_size); - - /* - * 3. if no such place exists, erase entire mrc-cache range & use - * block 0. First time around the erase is not needed, but this is a - * small overhead for simpler code. - */ - if (!cache) { - printk(BIOS_DEBUG, - "Need to erase the MRC cache region of %d bytes at %p\n", - cache_size, cache_base); - - flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); - - /* we will start at the beginning again */ - cache = cache_base; - } - // 4. write mrc data with flash->write() - printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", - cache); - flash->write(flash, to_flash_offset(flash, cache), - current->mrc_data_size + sizeof(*current), current); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); - -struct mrc_data_container *find_current_mrc_cache(void) -{ - struct mrc_data_container *cache_base; - u32 cache_size; - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return NULL; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - return find_current_mrc_cache_local(cache_base, cache_size); -} diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 3658bd8ec5..b05bf44657 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select INTEL_EDID select TSC_MONOTONIC_TIMER select INTEL_GMA_ACPI + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 5d49f5c671..17bbaffe3a 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -21,12 +21,10 @@ ramstage-y += smi.c ramstage-y += gma.c ramstage-y += acpi.c -ramstage-y += ../sandybridge/mrccache.c romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += early_init.c -romstage-y += ../sandybridge/mrccache.c romstage-y += ../../../arch/x86/walkcbfs.S smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index a2536ccc26..381bfbd763 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -593,8 +593,6 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ -struct mrc_data_container; -struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 9b90f36178..64f4a14c3f 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -18,6 +18,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI @@ -26,6 +27,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE bool select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 4a7a854bee..b1bc2ac223 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -22,7 +22,6 @@ ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-y += acpi.c -ramstage-y += mrccache.c romstage-y += ram_calc.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) @@ -36,7 +35,6 @@ mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc endif romstage-y += romstage.c -romstage-y += mrccache.c romstage-y += iommu.c romstage-y += early_init.c romstage-y += report_platform.c diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 116e0a8c7f..af5bd485e8 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -235,8 +235,6 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); #endif -struct mrc_data_container; -struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); |