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-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h1
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c20
2 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 88403e61ad..cccdf9736f 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -344,6 +344,7 @@ struct soc_amd_stoneyridge_gpio {
void sb_enable_rom(void);
void configure_stoneyridge_uart(void);
+void configure_stoneyridge_i2c(void);
void sb_clk_output_48Mhz(void);
void sb_disable_4dw_burst(void);
void sb_enable(device_t dev);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index c591c69d64..367c565486 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -320,6 +320,26 @@ void configure_stoneyridge_uart(void)
} while (!status);
}
+void configure_stoneyridge_i2c(void)
+{
+ bool status;
+
+ /* Power on the I2C devices */
+ power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C0);
+ power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C1);
+ power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C2);
+ power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C3);
+
+ /* Wait for the I2C devices to indicate power and clock OK */
+ do {
+ udelay(100);
+ status = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0);
+ status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1);
+ status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2);
+ status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3);
+ } while (!status);
+}
+
void sb_pci_port80(void)
{
u8 byte;