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-rw-r--r--src/mainboard/google/auron/Kconfig3
-rw-r--r--src/mainboard/google/jecht/Kconfig3
-rw-r--r--src/mainboard/intel/wtm2/Kconfig3
-rw-r--r--src/soc/intel/broadwell/Kconfig3
-rw-r--r--src/soc/intel/broadwell/northbridge.c4
5 files changed, 3 insertions, 13 deletions
diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index 5301e32571..45e4e3afb4 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -19,9 +19,6 @@ config BOARD_GOOGLE_BASEBOARD_AURON
if BOARD_GOOGLE_BASEBOARD_AURON
-config CHROMEOS
- select CHROMEOS_RAMOOPS_DYNAMIC
-
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select VBOOT_LID_SWITCH
diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig
index b04cc465fb..dac8f3bc81 100644
--- a/src/mainboard/google/jecht/Kconfig
+++ b/src/mainboard/google/jecht/Kconfig
@@ -14,9 +14,6 @@ config BOARD_GOOGLE_BASEBOARD_JECHT
if BOARD_GOOGLE_BASEBOARD_JECHT
-config CHROMEOS
- select CHROMEOS_RAMOOPS_DYNAMIC
-
config VBOOT
select VBOOT_VBNV_CMOS
diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig
index 7ac5f1c9aa..6312220266 100644
--- a/src/mainboard/intel/wtm2/Kconfig
+++ b/src/mainboard/intel/wtm2/Kconfig
@@ -11,9 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_LPC_TPM
select INTEL_INT15
-config CHROMEOS
- select CHROMEOS_RAMOOPS_DYNAMIC
-
config VBOOT
select VBOOT_VBNV_CMOS
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 7528c09fd3..bf84f7a2db 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -73,6 +73,9 @@ config BROADWELL_VBOOT_IN_BOOTBLOCK
binary is used meaning a jump is made from RW to the RO region
and back to the RW region after the binary is done.
+config CHROMEOS
+ select CHROMEOS_RAMOOPS_DYNAMIC
+
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK
diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c
index bc2638842a..f89552cc35 100644
--- a/src/soc/intel/broadwell/northbridge.c
+++ b/src/soc/intel/broadwell/northbridge.c
@@ -9,7 +9,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/acpi.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
@@ -372,9 +371,6 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
reserved_ram_resource(dev, index++, (0xc0000 >> 10),
(0x100000 - 0xc0000) >> 10);
- if (CONFIG(CHROMEOS))
- chromeos_reserve_ram_oops(dev, index++);
-
*resource_cnt = index;
}