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-rw-r--r--src/mainboard/pcengines/apu2/Kconfig10
-rw-r--r--src/vendorcode/amd/pi/00730F01/AGESA.h8
2 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
index 8c713e5f67..501d583c68 100644
--- a/src/mainboard/pcengines/apu2/Kconfig
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -114,4 +114,14 @@ config DIMM_SPD_SIZE
int
default 128
+config AGESA_USE_1_0_0_4_HEADER
+ bool
+ default y
+ help
+ Due to a bug in AGESA 1.0.0.A affecting boards without UMA, it is
+ impossible to use the newest blob. Using an older 1.0.0.4 blob
+ workarounds the problem, however some headers changes between blob
+ revisions. This option removes the changes in headers introduced
+ with AGESA 1.0.0.A to fit the 1.0.0.4 revision.
+
endif # BOARD_PCENGINES_APU2
diff --git a/src/vendorcode/amd/pi/00730F01/AGESA.h b/src/vendorcode/amd/pi/00730F01/AGESA.h
index c25b631cb2..5a3ee5b9f6 100644
--- a/src/vendorcode/amd/pi/00730F01/AGESA.h
+++ b/src/vendorcode/amd/pi/00730F01/AGESA.h
@@ -775,6 +775,7 @@ typedef enum {
DP_VS_0_4V_9_5DB = 0x18 ///< 0x18
} DP_FIXED_VOLT_SWING_TYPE;
+#if CONFIG(AGESA_USE_1_0_0_4_HEADER)
/// Alternative DRAM MAC
typedef enum {
MAC_UNTESTEDMAC, ///< Assign 0 to Untested MAC
@@ -785,6 +786,7 @@ typedef enum {
MAC_300k, ///< Assign 5 to 300k
MAC_200k, ///< Assign 6 to 200k
} DRAM_MAXIMUM_ACTIVATE_COUNT;
+#endif
// Macro for statically initializing various structures
#define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
@@ -1547,7 +1549,9 @@ typedef struct _CH_TIMING_STRUCT {
///< 667 (MHz)
///< 800 (MHz)
///< and so on...
+#if CONFIG(AGESA_USE_1_0_0_4_HEADER)
OUT UINT8 Mac; ///< Maximum Activate Count
+#endif
OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks)
OUT UINT8 Trcd; ///< DCT Trcd (busclocks)
OUT UINT8 Trp; ///< DCT Trp (busclocks)
@@ -1803,6 +1807,7 @@ typedef struct _MEM_PARAMETER_STRUCT {
///<
///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
+#if CONFIG(AGESA_USE_1_0_0_4_HEADER)
// Dram Mac Default
IN UINT8 DramMacDefault; ///< Default Maximum Activate Count
@@ -1818,6 +1823,7 @@ typedef struct _MEM_PARAMETER_STRUCT {
///< @BldCfgItem{BLDCFG_MEMORY_EXTENDED_TEMPERATURE_RANGE}
// Extended temperature range
+#endif
// Online Spare
IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
@@ -2721,8 +2727,10 @@ typedef struct {
IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving.
IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving.
IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down.
+#if CONFIG(AGESA_USE_1_0_0_4_HEADER)
IN UINT8 CfgMemoryMacDefault; ///< Memory DRAM MAC Default
IN BOOLEAN CfgMemoryExtendedTemperatureRange; ///< Memory Extended Temperature Range
+#endif
IN UINT32 CfgPowerDownMode; ///< Power Down Mode.
IN BOOLEAN CfgOnlineSpare; ///< Online Spare.
IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable.