diff options
35 files changed, 346 insertions, 218 deletions
diff --git a/src/Kconfig b/src/Kconfig index fd1ed1aa5a..461087d170 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -722,7 +722,7 @@ config ENABLE_APIC_EXT_ID config WARNINGS_ARE_ERRORS bool - default n + default y config ID_SECTION_OFFSET hex diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index a14c9f41f5..aedb2fd564 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -37,16 +37,16 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> /* - XMM map: - xmm1: cpu family - xmm2: fam10 comparison value - xmm3: backup ebx -*/ + * XMM map: + * xmm1: cpu family + * xmm2: fam10 comparison value + * xmm3: backup ebx + */ /* Save the BIST result */ movl %eax, %ebp - /*for normal part %ebx already contain cpu_init_detected from fallback call */ + /* for normal part %ebx already contain cpu_init_detected from fallback call */ cache_as_ram_setup: post_code(0xa0) @@ -113,7 +113,8 @@ cache_as_ram_setup: CAR_FAM10_out: /* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM. - Re-enable it in after RAM is initialized and before CAR is disabled */ + * Re-enable it in after RAM is initialized and before CAR is disabled + */ movl $0xc001102a, %ecx rdmsr bts $15, %eax diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c index 0eb461f4f8..5674c497d5 100644 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ b/src/cpu/amd/dualcore/dualcore_id.c @@ -47,7 +47,7 @@ static inline unsigned get_core_num(void) return (cpuid_ecx(0x80000008) & 0xff); } -static inline struct node_core_id get_node_core_id_x(void) +struct node_core_id get_node_core_id_x(void) { return get_node_core_id(read_nb_cfg_54()); // for pre_e0() nb_cfg_54 always be 0 diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 52fbdd2658..a499f5f0c4 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -417,7 +417,7 @@ static u32 is_core0_started(u32 nodeid) return htic; } -static void wait_all_core0_started(void) +void wait_all_core0_started(void) { /* When core0 is started, it will distingush_cpu_resets * So wait for that to finish */ diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index a318929609..d6f63933cb 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -326,7 +326,7 @@ static u32 is_core0_started(u32 nodeid) return htic; } -static void wait_all_core0_started(void) +void wait_all_core0_started(void) { /* When core0 is started, it will distingush_cpu_resets * So wait for that to finish */ diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index 7d09435214..be5dcb4bd5 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -74,7 +74,7 @@ static u32 get_core_num(void) } #endif -static struct node_core_id get_node_core_id_x(void) +struct node_core_id get_node_core_id_x(void) { return get_node_core_id(read_nb_cfg_54()); } diff --git a/src/include/cpu/amd/multicore.h b/src/include/cpu/amd/multicore.h index 5441c30cd3..5031ad98c0 100644 --- a/src/include/cpu/amd/multicore.h +++ b/src/include/cpu/amd/multicore.h @@ -32,6 +32,7 @@ struct node_core_id { #if defined(__GNUC__) // it can be used to get unitid and coreid it running only struct node_core_id get_node_core_id(u32 nb_cfg_54); +struct node_core_id get_node_core_id_x(void); #endif #if !defined(__PRE_RAM__) @@ -39,6 +40,7 @@ struct device; u32 get_apicid_base(u32 ioapic_num); void amd_sibling_init(struct device *cpu); #else +void wait_all_core0_started(void); void wait_all_other_cores_started(u32 bsp_apicid); void wait_all_aps_started(u32 bsp_apicid); void allow_all_aps_stop(u32 bsp_apicid); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 03086ec128..cbf8ef570b 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -57,7 +57,6 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "northbridge/amd/amdk8/early_ht.c" #include "superio/ite/it8712f/it8712f_early_serial.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "cpu/x86/mtrr/earlymtrr.c" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index bcead81e9e..e4762bfd09 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -123,9 +123,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ #include "southbridge/sis/sis966/sis966_early_setup_ss.h" -#include "southbridge/sis/sis966/sis966_early_setup_car.c" - - #include "cpu/amd/car/post_cache_as_ram.c" diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index e7de603960..ed8ee85647 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -30,10 +30,11 @@ //used by raminit #define QRANK_DIMM_SUPPORT 1 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 +// used by init_cpus and fidvid (disabled until someone tests this) +// #define SET_FIDVID 1 +#define SET_FIDVID 0 +// if we want to wait for core1 done before DQS training, set it to 0 +// #define SET_FIDVID_CORE0_ONLY 1 #include <stdint.h> #include <string.h> @@ -121,7 +122,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "cpu/amd/model_fxx/fidvid.c" +// Disabled until it's actually used: +// #include "cpu/amd/model_fxx/fidvid.c" #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 472e55594f..80b956ac07 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1179,6 +1179,14 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base); void setup_resource_map_x(const u32 *register_values, u32 max); + +/* reset_test.c */ +u32 cpu_init_detected(u8 nodeid); +u32 bios_reset_detected(void); +u32 cold_reset_detected(void); +u32 other_reset_detected(void); +u32 get_sblk(void); +u8 get_sbbusn(u8 sblk); #endif #endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/amdfam10_conf.c b/src/northbridge/amd/amdfam10/amdfam10_conf.c index 4ce3e9a471..adfff0f6e3 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_conf.c +++ b/src/northbridge/amd/amdfam10/amdfam10_conf.c @@ -61,6 +61,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } +#if CONFIG_AMDMCT == 0 static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) { u32 i; @@ -117,8 +118,9 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) pci_write_config32(dev, 0x124, d.mask>>8); } +#endif - +#if CONFIG_AMDMCT == 0 static void set_DctSelBaseAddr(u32 i, u32 sel_m) { device_t dev; @@ -152,7 +154,6 @@ static u32 get_DctSelBaseAddr(u32 i) return sel_m; } -#if CONFIG_AMDMCT == 0 #ifdef UNUSED_CODE static void set_DctSelHiEn(u32 i, u32 val) { @@ -234,6 +235,7 @@ static u32 get_one_DCT(struct mem_info *meminfo) return one_DCT; } + #if CONFIG_HW_MEM_HOLE_SIZEK != 0 // See that other copy in northbridge.c static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes) @@ -574,7 +576,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, } #endif - +#ifdef UNUSED_CODE static void re_set_all_config_map_reg(u32 nodes, u32 segbit, sys_info_conf_t *sysinfo) { @@ -616,7 +618,7 @@ static void re_set_all_config_map_reg(u32 nodes, u32 segbit, } } - +#endif static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) { @@ -660,7 +662,7 @@ static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, } - +#ifdef UNUSED_CODE static void set_BusSegmentEn(u32 node, u32 segbit) { #if CONFIG_PCI_BUS_SEGN_BITS @@ -679,6 +681,7 @@ static void set_BusSegmentEn(u32 node, u32 segbit) pci_write_config32(dev, 0x68, dword); #endif } +#endif #if !defined(__PRE_RAM__) static u32 get_io_addr_index(u32 nodeid, u32 linkn) diff --git a/src/northbridge/amd/amdfam10/amdfam10_pci.c b/src/northbridge/amd/amdfam10/amdfam10_pci.c index bc1bde08d0..d08a9718c7 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_pci.c +++ b/src/northbridge/amd/amdfam10/amdfam10_pci.c @@ -32,6 +32,7 @@ static u32 pci_read_config32_index(device_t dev, u32 index_reg, u32 index) return dword; } +#ifdef UNUSED_CODE static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 data) { @@ -40,6 +41,7 @@ static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 pci_write_config32(dev, index_reg + 0x4, data); } +#endif static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index) { @@ -55,6 +57,7 @@ static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index) return dword; } +#ifdef UNUSED_CODE static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index, u32 data) { @@ -69,5 +72,6 @@ static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index } #endif +#endif diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index fc89ba39c4..f87428ba0c 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -17,12 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + +#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */ static void print_tx(const char *strval, u32 val) { #if CONFIG_DEBUG_RAM_SETUP printk(BIOS_DEBUG, "%s%08x\n", strval, val); #endif } +#endif static void print_t(const char *strval) { diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 69869bf48c..21e06d1e2e 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -29,7 +29,7 @@ /* mmconf is not ready */ /* io_ext is not ready */ -static u32 cpu_init_detected(u8 nodeid) +u32 cpu_init_detected(u8 nodeid) { u32 htic; device_t dev; @@ -40,7 +40,7 @@ static u32 cpu_init_detected(u8 nodeid) return !!(htic & HTIC_INIT_Detect); } -static u32 bios_reset_detected(void) +u32 bios_reset_detected(void) { u32 htic; htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); @@ -48,7 +48,7 @@ static u32 bios_reset_detected(void) return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); } -static u32 cold_reset_detected(void) +u32 cold_reset_detected(void) { u32 htic; htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); @@ -56,7 +56,7 @@ static u32 cold_reset_detected(void) return !(htic & HTIC_ColdR_Detect); } -static u32 other_reset_detected(void) // other warm reset not started by BIOS +u32 other_reset_detected(void) // other warm reset not started by BIOS { u32 htic; htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); @@ -154,7 +154,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b return 0; } -static u32 get_sblk(void) +u32 get_sblk(void) { u32 reg; /* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */ @@ -163,7 +163,7 @@ static u32 get_sblk(void) } -static u8 get_sbbusn(u8 sblk) +u8 get_sbbusn(u8 sblk) { return node_link_to_bus(0, sblk); } diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index cc970c5906..dc7ef1bcab 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -11,6 +11,7 @@ #ifdef __PRE_RAM__ void showallroutes(int level, device_t dev); void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base); +void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr); #endif #endif /* AMDK8_H */ diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 5db9deafc4..91ff6b00ee 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -576,7 +576,7 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num) return reset_needed; } -#if defined(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) || defined(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55) +#if defined(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) // || defined(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55) static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val) { uint32_t dword; diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 8217464e37..efb7738306 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -19,7 +19,7 @@ #define QRANK_DIMM_SUPPORT 0 #endif -static void setup_resource_map(const unsigned int *register_values, int max) +void setup_resource_map(const unsigned int *register_values, int max) { int i; // printk(BIOS_DEBUG, "setting up resource map...."); @@ -2346,7 +2346,7 @@ static void set_sysinfo_in_ram(unsigned val) { } -static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, +void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr) { int i; diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h index 8897ee71fa..7a548daf3b 100644 --- a/src/northbridge/amd/amdk8/raminit.h +++ b/src/northbridge/amd/amdk8/raminit.h @@ -13,6 +13,7 @@ struct mem_controller { struct sys_info; void exit_from_self(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo); +void setup_resource_map(const unsigned int *register_values, int max); #if defined(__PRE_RAM__) && defined(RAMINIT_SYSINFO) && RAMINIT_SYSINFO == 1 void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo); diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 6652783e66..01241f05c8 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -74,7 +74,7 @@ */ -static void setup_resource_map(const unsigned int *register_values, int max) +void setup_resource_map(const unsigned int *register_values, int max) { int i; for (i = 0; i < max; i += 3) { @@ -3206,7 +3206,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, } -static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, +void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr) { int i; diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 36cb7cbea2..167088f200 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -22,7 +22,9 @@ static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); +#ifdef UNUSED_CODE static u32 GetScrubAddr_D(u32 Node); +#endif static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); @@ -249,7 +251,7 @@ static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, } } - +#ifdef UNUSED_CODE static u32 GetScrubAddr_D(u32 Node) { /* Get the current 40-bit Scrub ADDR address, scaled to 32-bits, @@ -280,7 +282,7 @@ static u32 GetScrubAddr_D(u32 Node) return val; /* ScrubAddr[39:8] */ } - +#endif static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat) { diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index 1724ca0640..a2d08d194e 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -313,7 +313,8 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct) } } - +#ifdef UNUSED_CODE +/* Callback not required */ static u8 mct_AdjustDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) { u8 skip = 0; @@ -323,7 +324,7 @@ static u8 mct_AdjustDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) return skip; } - +#endif static u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 DQSDelay, diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index b6bd6dfa38..cc49aad2ae 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -19,6 +19,7 @@ /* Call-backs */ #include <delay.h> + static u16 mctGet_NVbits(u8 index) { u16 val = 0; @@ -411,6 +412,7 @@ static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTSt #endif } +#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val) { if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) { @@ -420,6 +422,7 @@ static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStr } return val; } +#endif static void mctHookAfterAnyTraining(void) { @@ -430,8 +433,9 @@ static u32 mctGetLogicalCPUID_D(u8 node) return mctGetLogicalCPUID(node); } +#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */ static u8 mctSetNodeBoundary_D(void) { return 0; } - +#endif diff --git a/src/northbridge/intel/i3100/i3100.h b/src/northbridge/intel/i3100/i3100.h index bbdad3f3c1..8aae1a9aed 100644 --- a/src/northbridge/intel/i3100/i3100.h +++ b/src/northbridge/intel/i3100/i3100.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __I3100_H__ +#define __I3100_H__ + #define IURBASE 0X14 #define MCHCFG0 0X50 #define MCHSCRB 0X52 @@ -60,3 +63,10 @@ /* DRC */ #define DRC_NOECC_MODE (0 << 20) #define DRC_72BIT_ECC (1 << 20) + + +#ifdef __GNUC__ +int bios_reset_detected(void); +#endif + +#endif diff --git a/src/northbridge/intel/i3100/reset_test.c b/src/northbridge/intel/i3100/reset_test.c index 9cf4d89d7e..de86f8024d 100644 --- a/src/northbridge/intel/i3100/reset_test.c +++ b/src/northbridge/intel/i3100/reset_test.c @@ -6,7 +6,7 @@ /* To see if I have already booted I check to see if memory * has been enabled. */ -static int bios_reset_detected(void) +int bios_reset_detected(void) { uint32_t dword; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index 5f7f94f5e2..c06a961ffd 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -3,6 +3,13 @@ #include "chip.h" +#ifndef __PRE_RAM__ void bcm5785_enable(device_t dev); +#else +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +#endif + +void ldtstop_sb(void); +unsigned get_sbdn(unsigned bus); #endif /* BCM5785_H */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c index 62e004dac3..41b4ca3a10 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c @@ -4,6 +4,7 @@ */ #include <reset.h> +#include "bcm5785.h" #include "bcm5785_enable_rom.c" static void bcm5785_enable_lpc(void) @@ -53,12 +54,12 @@ static void bcm5785_enable_wdt_port_cf9(void) pci_write_config8(dev, 0x40, (1<<2)); } -static unsigned get_sbdn(unsigned bus) +unsigned get_sbdn(unsigned bus) { device_t dev; /* Find the device. - * There can only be one 8111 on a hypertransport chain/bus. + * There can only be one bcm5785 on a hypertransport chain/bus. */ dev = pci_locate_device_on_bus( PCI_ID(0x1166, 0x0036), @@ -70,7 +71,7 @@ static unsigned get_sbdn(unsigned bus) #define SB_VFSMAF 0 -static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { //ACPI Decode Enable outb(0x0e, 0xcd6); @@ -89,7 +90,7 @@ static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) outb(9, 0xcd7); } -static void ldtstop_sb(void) +void ldtstop_sb(void) { outb(1, 0x2060); } diff --git a/src/southbridge/intel/i82801ax/i82801ax_smbus.h b/src/southbridge/intel/i82801ax/i82801ax_smbus.h index 06d987721f..d3f49f9a71 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_smbus.h +++ b/src/southbridge/intel/i82801ax/i82801ax_smbus.h @@ -113,8 +113,6 @@ static int do_smbus_read_byte(unsigned device, unsigned address) static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { - unsigned char global_control_register; - unsigned char global_status_register; unsigned char byte; unsigned char stat; int i; diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.h b/src/southbridge/intel/i82801bx/i82801bx_smbus.h index 5586ac752c..a873958833 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_smbus.h +++ b/src/southbridge/intel/i82801bx/i82801bx_smbus.h @@ -51,6 +51,7 @@ static int smbus_wait_until_done(void) return loops ? 0 : -1; } +#ifdef UNUNSED_CODE static int smbus_wait_until_blk_done(void) { unsigned loops = SMBUS_TIMEOUT; @@ -63,6 +64,7 @@ static int smbus_wait_until_blk_done(void) } while ((byte & (1 << 7)) == 0); return loops ? 0 : -1; } +#endif static int do_smbus_read_byte(unsigned device, unsigned address) { @@ -110,3 +112,69 @@ static int do_smbus_read_byte(unsigned device, unsigned address) return byte; } +#ifdef UNUNSED_CODE +static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, + unsigned data1, unsigned data2) +{ + unsigned char byte; + unsigned char stat; + int i; + + print_err("Untested smbus_write_block called\n"); + + /* Clear the PM timeout flags, SECOND_TO_STS */ + outw(inw(PMBASE_ADDR + 0x66), PMBASE_ADDR + 0x66); + + if (smbus_wait_until_ready() < 0) { + return -2; + } + + /* Setup transaction */ + /* Obtain ownership */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + for (stat = 0; (stat & 0x40) == 0;) { + stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } + /* Clear the done bit */ + outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); + + /* Set the command address */ + outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + + /* Set the block length */ + outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Try sending out the first byte of data here */ + byte = (data1 >> (0)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + /* Issue a block write command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, + SMBUS_IO_BASE + SMBHSTCTL); + + for (i = 0; i < length; i++) { + /* Poll for transaction completion */ + if (smbus_wait_until_blk_done() < 0) { + return -3; + } + + /* Load the next byte */ + if (i > 3) + byte = (data2 >> (i % 4)) & 0x0ff; + else + byte = (data1 >> (i)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + + /* Clear the done bit */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + SMBUS_IO_BASE + SMBHSTSTAT); + } + + print_debug("SMBUS Block complete\n"); + return 0; +} +#endif diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 2f6e9d284f..687232f302 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -24,6 +24,9 @@ #include "chip.h" +#ifndef __PRE_RAM__ void mcp55_enable(device_t dev); - +#else +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +#endif #endif /* MCP55_H */ diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c b/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c index 3b5a507538..5c5f07c81a 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c @@ -20,6 +20,7 @@ */ #include <reset.h> +#include "mcp55.h" static unsigned get_sbdn(unsigned bus) { @@ -52,7 +53,7 @@ void hard_reset(void) outb(0x0e, 0x0cf9); } -static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { /* default value for mcp55 is good */ /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ diff --git a/src/southbridge/sis/sis966/sis966_early_setup_car.c b/src/southbridge/sis/sis966/sis966_early_setup_car.c index 2f7569ee3b..9de33137a7 100644 --- a/src/southbridge/sis/sis966/sis966_early_setup_car.c +++ b/src/southbridge/sis/sis966/sis966_early_setup_car.c @@ -21,7 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) +void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) { uint32_t tgio_ctrl; uint32_t pll_ctrl; diff --git a/src/southbridge/sis/sis966/sis966_early_smbus.c b/src/southbridge/sis/sis966/sis966_early_smbus.c index 3d4954b64f..1c81bf16fd 100644 --- a/src/southbridge/sis/sis966/sis966_early_smbus.c +++ b/src/southbridge/sis/sis966/sis966_early_smbus.c @@ -23,6 +23,174 @@ #define SMBUS0_IO_BASE 0x8D0 +static inline void smbus_delay(void) +{ + outb(0x80, 0x80); +} + +int smbus_wait_until_ready(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) { + return 0; + } + outb(val,smbus_io_base + SMBHSTSTAT); + } while(--loops); + return -2; +} + +int smbus_wait_until_done(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + + val = inb(smbus_io_base + 0x00); + if ( (val & 0xff) != 0x02) { + return 0; + } + } while(--loops); + return -3; +} + +int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) +{ + unsigned char global_status_register; + unsigned char byte; + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); + smbus_delay(); + + /* byte data recv */ + outb(0x05, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD); + + if (global_status_register != 0x80) { // lose check, otherwise it should be 0 + return -1; + } + return byte; +} + +int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) +{ + unsigned global_status_register; + + outb(val, smbus_io_base + SMBHSTDAT0); + smbus_delay(); + + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + smbus_delay(); + + /* set up for a byte data write */ + outb(0x04, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + + if (global_status_register != 0x80) { + return -1; + } + return 0; +} + +static inline int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + outb(0xff, smbus_io_base + 0x00); + smbus_delay(); + outb(0x20, smbus_io_base + 0x03); + smbus_delay(); + + outb(((device & 0x7f) << 1)|1 , smbus_io_base + 0x04); + smbus_delay(); + outb(address & 0xff, smbus_io_base + 0x05); + smbus_delay(); + outb(0x12, smbus_io_base + 0x03); + smbus_delay(); + +int i,j; +for(i=0;i<0x1000;i++) +{ + if (inb(smbus_io_base + 0x00) != 0x08) + { smbus_delay(); + for(j=0;j<0xFFFF;j++); + } +}; + + global_status_register = inb(smbus_io_base + 0x00); + byte = inb(smbus_io_base + 0x08); + + if (global_status_register != 0x08) { // lose check, otherwise it should be 0 + print_debug("Fail");print_debug("\r\t"); + return -1; + } + print_debug("Success");print_debug("\r\t"); + return byte; +} + + +static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) +{ + unsigned global_status_register; + + outb(val, smbus_io_base + SMBHSTDAT0); + smbus_delay(); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + smbus_delay(); + + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* set up for a byte data write */ + outb(0x06, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + + if (global_status_register != 0x80) { + return -1; + } + return 0; +} + + + static const uint8_t SiS_LPC_init[34][3]={ {0x04, 0xF8, 0x07}, //Reg 0x04 {0x45, 0x00, 0x00}, //Reg 0x45 //Enable Rom Flash @@ -564,11 +732,11 @@ static void enable_smbus(void) printk(BIOS_DEBUG, "enable_smbus <--------\n"); } -static int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS0_IO_BASE, device, address); } -static int smbus_write_byte(unsigned device, unsigned address, unsigned char val) +int smbus_write_byte(unsigned device, unsigned address, unsigned char val) { return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val); } diff --git a/src/southbridge/sis/sis966/sis966_smbus.h b/src/southbridge/sis/sis966/sis966_smbus.h index 3294be5899..087ea47f23 100644 --- a/src/southbridge/sis/sis966/sis966_smbus.h +++ b/src/southbridge/sis/sis966/sis966_smbus.h @@ -37,166 +37,10 @@ */ #define SMBUS_TIMEOUT (100*1000*10) -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) { - return 0; - } - outb(val,smbus_io_base + SMBHSTSTAT); - } while(--loops); - return -2; -} - -static int smbus_wait_until_done(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - - val = inb(smbus_io_base + 0x00); - if ( (val & 0xff) != 0x02) { - return 0; - } - } while(--loops); - return -3; -} -static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) -{ - unsigned char global_status_register; - unsigned char byte; - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* byte data recv */ - outb(0x05, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); - - if (global_status_register != 0x80) { // lose check, otherwise it should be 0 - return -1; - } - return byte; -} -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) -{ - unsigned global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* set up for a byte data write */ - outb(0x04, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; - - if (global_status_register != 0x80) { - return -1; - } - return 0; -} -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) -{ - unsigned char global_status_register; - unsigned char byte; - - outb(0xff, smbus_io_base + 0x00); - smbus_delay(); - outb(0x20, smbus_io_base + 0x03); - smbus_delay(); - - outb(((device & 0x7f) << 1)|1 , smbus_io_base + 0x04); - smbus_delay(); - outb(address & 0xff, smbus_io_base + 0x05); - smbus_delay(); - outb(0x12, smbus_io_base + 0x03); - smbus_delay(); - -int i,j; -for(i=0;i<0x1000;i++) -{ - if (inb(smbus_io_base + 0x00) != 0x08) - { smbus_delay(); - for(j=0;j<0xFFFF;j++); - } -}; - - global_status_register = inb(smbus_io_base + 0x00); - byte = inb(smbus_io_base + 0x08); - - if (global_status_register != 0x08) { // lose check, otherwise it should be 0 - print_debug("Fail");print_debug("\r\t"); - return -1; - } - print_debug("Success");print_debug("\r\t"); - return byte; -} - - -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) -{ - unsigned global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* set up for a byte data write */ - outb(0x06, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; - - if (global_status_register != 0x80) { - return -1; - } - return 0; -} +int smbus_wait_until_ready(unsigned smbus_io_base); +int smbus_wait_until_done(unsigned smbus_io_base); +int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device); +int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val); +int smbus_read_byte(unsigned device, unsigned address); +int smbus_write_byte(unsigned device, unsigned address, unsigned char val); diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c index 037f5a75eb..aa224a9469 100644 --- a/src/southbridge/via/k8t890/k8t890_early_car.c +++ b/src/southbridge/via/k8t890/k8t890_early_car.c @@ -113,7 +113,7 @@ u8 k8t890_early_setup_ht(void) return 1; } -static int s3_save_nvram_early(u32 dword, int size, int nvram_pos) +static inline int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); @@ -134,7 +134,7 @@ static int s3_save_nvram_early(u32 dword, int size, int nvram_pos) return nvram_pos; } -static int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) +static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { switch (size) { case 1: |